VLDB 2026 Research / reviewers in the wild / expert
An Pan
dblp:94/1981
· DBLP profile ↗
6ranked-venue papers
0as first author
3since 2021 · last 2026
0000-0002-1089-7945ORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Artificial intelligence and machine learning · 2 · 1 since 2021Systems, architecture and hardware · 2Graphics, computer vision, multimedia, augmented reality and games · 2 · 2 since 2021Applied, interdisciplinary, general and emerging computing · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Artificial intelligence
1 paper |
Autonomous driving · 67% 3D vision · 33% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Integrated circuit design · 100% |
Topics — the 6 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Computer vision › 3D vision › 3d scene understanding › semantic scene completion
4d occupancy forecasting |
1.0 | 1 | 2026 | SparseWorld: A Flexible, Adaptive, and Efficient 4D Occupancy World Model Powered by Sparse and Dynamic Queries · AAAI 2026 |
Robotics › Autonomous driving › driving scene understanding
occupancy world model |
1.0 | 1 | 2026 | SparseWorld: A Flexible, Adaptive, and Efficient 4D Occupancy World Model Powered by Sparse and Dynamic Queries · AAAI 2026 |
Robotics › Autonomous driving
perception and prediction |
1.0 | 1 | 2026 | SparseWorld: A Flexible, Adaptive, and Efficient 4D Occupancy World Model Powered by Sparse and Dynamic Queries · AAAI 2026 |
Integrated circuit design
digital circuit design |
0.3 | 1 | 2018 | A Subthreshold Baseband Processor Core Design With Custom Modules and Cells for Passive RFID Tags · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2018 |
Integrated circuit design › low-power circuit design
subthreshold circuit design |
0.3 | 1 | 2018 | A Subthreshold Baseband Processor Core Design With Custom Modules and Cells for Passive RFID Tags · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2018 |
Internet of things and sensor networks › RFID systems › passive RFID
passive RFID tags |
0.1 | 1 | 2018 | A Subthreshold Baseband Processor Core Design With Custom Modules and Cells for Passive RFID Tags · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2018 |
Methods — techniques the papers use, named apart from their topics
temporal-spatial attention · 1.0sparse queries · 1.0regression-guided forecasting · 1.0ratioed logic · 0.7double-edge-triggered flip-flop · 0.7custom logic cell design · 0.7
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | SparseWorld: A Flexible, Adaptive, and Efficient 4D Occupancy World Model Powered by Sparse and Dynamic QueriesabstractSemantic occupancy has emerged as a powerful representation in world models for its ability to capture rich spatial semantics. However, most existing occupancy world models rely on static and fixed embeddings or grids, which inherently limit the flexibility of perception. Moreover, their ``in-place classification" over grids exhibits a potential misalignment with the dynamic and continuous nature of real scenarios. In this paper, we propose SparseWorld, a novel 4D occupancy world model that is flexible, adaptive, and efficient, powered by sparse and dynamic queries. We propose a Range-Adaptive Perception module, in which learnable queries are modulated by the ego vehicle states and enriched with temporal-spatial associations to enable extended-range perception. To effectively capture the dynamics of the scene, we design a State-Conditioned Forecasting module, which replaces classification-based forecasting with regression-guided formulation, precisely aligning the dynamic queries with the continuity of the 4D environment. In addition, We specifically devise a Temporal-Aware Self-Scheduling training strategy to enable smooth and efficient training. Extensive experiments demonstrate that SparseWorld achieves state-of-the-art performance across perception, forecasting, and planning tasks. Comprehensive visualizations and ablation studies further validate the advantages of SparseWorld in terms of flexibility, adaptability, and efficiency. Chenxu Dang, Jason Bao, Pei An, Xinyue Tang, An Pan, Jie Ma 0003, Bingchuan Sun |
AAAI | 6 |
| 2026 | Cross-ancestry information transfer framework improves protein abundance prediction and protein-trait association identificationabstractGenetics-informed proteome-wide association studies (PWASs) provide an effective way to uncover proteomic mechanisms underlying complex diseases. PWAS relies on an ancestry-matched reference panel to model the impact of genetically determined protein expression on phenotype. However, reference panels from underrepresented populations remain relatively limited. We developed a multi-ancestry framework to enhance protein prediction in these populations by integrating diverse information-sharing strategies into a Multi-Ancestry Best-performing Model (MABM). Results indicated that MABM increased the prediction performance with higher performance observed in both cross-validation and an external dataset. Leveraging the Biobank Japan, we identified three times as many significant PWAS associations using MABM as using Lasso model. Notably, 47.5% of the MABM specific associations were reproduced in independent East Asian datasets with concordant effect sizes. Furthermore, MABM enhanced decision-making in gene/protein prioritization for functional validation for complex traits by validating well-established associations and uncovering novel trait-related candidates. The benefits of MABM were further validated in additional ancestries and demonstrated in brain tissue-based PWAS, underscoring its broad applicability. Our findings close critical gaps in multi-omics research among underrepresented populations and facilitate trait-relevant protein discovery in underrepresented populations. Wenli Zhai, Lingyun Sun, Wenwei Fang, Yidan Dong, Chunxiao Cheng, Yuanjiao Liu, Jiadong Ji, An Pan, Eric R. Gamazon, Xiong-Fei Pan |
Briefings Bioinform. | 10 |
| 2025 | A decoder-free feature aggregation network for medical image segmentation
Jiajia Ni, An Pan |
Multim. Tools Appl. | 3 |
| 2019 | Optimal sensor placement based on relaxation sequential algorithm
Kangli Dong, An Pan, Zhenrui Peng, Zhaoyuan Jiang, Shaoyuan Li |
Neurocomputing | 3 |
| 2018 | A Subthreshold Baseband Processor Core Design With Custom Modules and Cells for Passive RFID TagsabstractSophisticated subthreshold passive radio frequency identification tag's baseband processor (BBP) core design for ultralow-power Internet of Things end devices is presented in this paper. Custom logic cells and tailored logic architectures are applied to eliminate timing violations when the operating voltage is much lower than nominal level. For the consideration of limited availability of radio frequency power, power-aware scheme is applied to the key modules, including PIE decoding and command receiving. Furthermore, Galois linear feedback shift register and double-edge-triggered techniques help to improve clock efficiency and reduce the impact of frequency variation in data link portions. Importantly, a novel custom ratioed logic style is adopted in key modules to fundamentally speed up signals' propagation at ultralow-voltage. The proposed BBP was fabricated in 90-nm CMOS as well as the regular design with the same function. It was also implemented in the tag chip's fabrication. In measurement the proposed design indicates good robustness and is much more competent for subthreshold operation. It can operate below 0.3 V with power consumption below 130 nW. Weiwei Shi 0001, An Pan, Oliver Chiu-sing Choy |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 2 |
| 2010 | An Area-Efficient and Low-Power Multirate Decoder for Quasi-Cyclic Low-Density Parity-Check CodesabstractThe quasi-cyclic low-density parity-check (QC-LDPC) codes are widely applied in digital broadcast and communication systems. However, the decoders are still difficult to be put into practice due to their large area and high power, especially in the wireless mobile devices. This paper presents an improved all-purpose multirate iterative decoder architecture for QC-LDPC codes, which can largely reduce their area and power. The architecture implements the normalized min-sum algorithm, rearranges the original two-phase message-passing flow, and adopts an efficient quantization method for the second minimum absolute values, an optimized storing scheme for the position indexes and signs, and an elaborate clock gating technique for substantive memories and registers. It is also configurable for any regular and irregular QC-LDPC codes, and can be easily tuned up to different code rates and code word lengths. The chip is fabricated in an SMIC 0.18- six-metal-layer standard CMOS technology. It attains a throughput of 104.5 Mb/s, and dissipates an average power of 486 mW at 125 MHz, and 15 decoding iterations. The core area is only 9.76 mm2. The chip has been applied into the China digital terrestrial/television multimedia broadcasting system. Bo Xiang, An Pan, Dan Bao, Xiaoyang Zeng |
IEEE Trans. Very Large Scale Integr. Syst. | 3 |