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Masao Mizukami

dblp:94/2107 · DBLP profile ↗
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3ranked-venue papers
0as first author
0since 2021 · last 1996
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Computer networks · 3

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer networks
2 papers
Optical networks · 60% Internet architecture and protocols · 20% Routing and switching · 20%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Interconnection networks and networks-on-chip · 62% Integrated circuit design · 38%

Topics — the 10 heaviest of 10, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Optical networks › optical communication components
optical add-drop multiplexer		 0.011996
A High Prformance Switch for OC-12 SONET Self-Healing Ring Networks · IEEE J. Sel. Areas Commun. 1996
Optical networks › network survivability
self-healing ring		 0.011996
A High Prformance Switch for OC-12 SONET Self-Healing Ring Networks · IEEE J. Sel. Areas Commun. 1996
Optical networks › optical transmission
SONET		 0.011996
A High Prformance Switch for OC-12 SONET Self-Healing Ring Networks · IEEE J. Sel. Areas Commun. 1996
Routing and switching › switching networks
space-division switching		 0.011996
A High Prformance Switch for OC-12 SONET Self-Healing Ring Networks · IEEE J. Sel. Areas Commun. 1996
Internet architecture and protocols › ATM networks
ATM switching		 0.011991
32 x 32 Shared Buffer Type ATM Switch VLSI's for B-ISDN's · IEEE J. Sel. Areas Commun. 1991
Internet architecture and protocols › ISDN
broadband ISDN		 0.011991
32 x 32 Shared Buffer Type ATM Switch VLSI's for B-ISDN's · IEEE J. Sel. Areas Commun. 1991
Interconnection networks and networks-on-chip › switch architecture
ATM switch		 0.011991
32 x 32 Shared Buffer Type ATM Switch VLSI's for B-ISDN's · IEEE J. Sel. Areas Commun. 1991
Integrated circuit design › VLSI design
CMOS VLSI		 0.011991
32 x 32 Shared Buffer Type ATM Switch VLSI's for B-ISDN's · IEEE J. Sel. Areas Commun. 1991
Interconnection networks and networks-on-chip
multicast		 0.011991
32 x 32 Shared Buffer Type ATM Switch VLSI's for B-ISDN's · IEEE J. Sel. Areas Commun. 1991
Interconnection networks and networks-on-chip
switch architecture		 0.011991
32 x 32 Shared Buffer Type ATM Switch VLSI's for B-ISDN's · IEEE J. Sel. Areas Commun. 1991

Methods — techniques the papers use, named apart from their topics

parallel processing architecture · 0.0VLSI design · 0.0
YearPublicationVenuePosition
1996 A High Prformance Switch for OC-12 SONET Self-Healing Ring Networks
abstract
The progress of ITU-T and ANSI standards on SDH/SONET is accelerating the evolution of transmission systems all over the world. The advanced operation administration and maintenance (OAM) functions it provides makes it possible to create a self healing ring network which protects against failure. This self-healing ring consists of add/drop multiplexers (ADM's). The switch in the ADM plays an important role in achieving self-healing operation. In this paper, self-healing ring architecture and operations are analyzed in order to determine the requirements for the ADM switch. On the basis of this result, new space division switching methods, which significantly reduce the amount of hardware needed, are proposed. A parallel processing architecture which makes it possible to develop a low-cost large-scale switch is also devised. Finally, a developed switch LSI chip is presented. Combining two identical chips with the proposed parallel processing architecture, a 32/spl times/32 STS-3 switch (5 Gb/s throughput) with an STS-1 time slot interchange (TSI) function is realized.
Masahiro Takatori, Yukio Nakano, Yoshihiro Ashi, Hiroyuki Fujita, Masao Mizukami, Kunihiro Itoh
 IEEE J. Sel. Areas Commun.5
1991 32 x 32 Shared Buffer Type ATM Switch VLSI's for B-ISDN's
abstract
A set of 0.8 mu m CMOS VLSIs developed for shared buffer switches in asynchronous transfer mode (ATM) switching systems is described. A 32*32 unit switch consists of eight buffer memory VLSIs, two memory control VLSIs, and two commercially available first in first out (FIFO) memory LSIs. Using the VLSIs, the switch can be mounted on a printed board. To provide excellent traffic characteristics not only under random traffic conditions but also under burst traffic conditions, this switch has a 2-Mb shared buffer memory, the largest reported to date. which can save 4096 cells among 32 output ports. This switch has a priority control function to meet the different cell loss rate requirements and switching delay requirements of different service classes. A multicast function and a 600 Mb/s link switch architecture, which are suitable for ATM network systems connecting various media, and an expansion method using the 32*32 switching board to achieve large-scale switching systems such as 256*256 or 1024*1024 switches are discussed.>
Takahiko Kozaki, Noboru Endo, Yoshito Sakurai, Osamu Matsubara, Masao Mizukami, Ken'ichi Asano
 IEEE J. Sel. Areas Commun.5
1984 High Speed Encoding and Decoding Processor for Group 4 Facsimile Apparatus
Koozoo Nakamura, Yasuyuki Kojima, Nagaharu Hamada, Tatsuki Inuzuka, Noboru Suemori, Masao Mizukami
 ICC (1)6