This paper presents analysis and synthesis techniques for multicomputer networks that perform fast reconfiguration into rings, stars, and trees. Each reconfiguration into a new network structure requires only two codes (reconfiguration code RC and bias B), and can be performed during one clock period. Because the reconfiguration methodology presented is based on some fine mathematical properties exhibited by special shift registers with variable bias (SRVB), they are also introduced in this paper.

The objective of this paper is to develop fast techniques of data exchange optimization with the use of reconfigurable binary trees.

This paper discusses efficient communication algorithms for multicomputer networks organized as reconfigurable binary trees.

For associative processing and relational data bases characterized by sequential memory search, it is convenient to store a sequence of data files in a content-addressable memory since it can perform two concurrent data base operations at a time (search and update, search and delete, etc.) and the sequential nature of its operation is in conformity with the sequential nature of maintenance and update of data files. To take into account various communication delays introduced by the communication network in transferring updated words to the content-adressable memory assume that a sequence of data words contained in the same data file is stored with a shifting distance from one another, d ≥ 1, where the d integer is selectable by a programmer, and a pair of adjacent data words from the same file may have a constant or variable d. (A particular case, d = 1, means consecutive word storage.) In this paper, we discuss various memory allocation algorithms that allow formation of a multiprocessor system that incorporates several content-addressable memories and is designated for fast data base applications. All memory allocation schemes introduced in this paper are described by a Diophantine equation whose solution, x, shows the distance between any two processors that are not in conflict when they access the same content-addressable memory. The paper presents a technique for finding a maximal set of noninterfering processors and conflict-free allocation techniques for various structures of data files.

This paper elaborates on basic software techniques for distributing the hardware resource among user programs computed by a multicomputer system with a dynamic architecture. The system can switch the hardware resources into the minimal sized computers required for computations and initiate the unused resources into execution of additional program streams. Thus it maximizes the number of parallel program streams computed by the same set of resources.

This paper considers basic concepts of designing a Supersystem with dynamic architecture.

This paper considers the organization of certain multicomputer systems with a particular type of dynamic architecture. The system allows one to reconfigure via software available hardware resources (widths of processors, memories, and I/O units), forming computers with different word sizes. A multicomputer system is formed from identical dynamic computer groups. Each group may assume a variety of architectural states which are distinct from each other by the number and sizes of concurrent computers. To construct one dynamic computer group, one uses a universal building module, an 8-bit microprocessor on an LSI chip, and standard memory units. This paper considers basic principles of dynamic computer group implementation: organization of parallel (for words) and serial (for instructions) exchange between primary memory and processor, automatic variation of the time intervals assigned for operations which are executed in differently sized computers, formation of the processor with variable word size, switching from one architectural state to another, scheduling of the memory, and task synchronization.

This paper discusses some important software problems arising in dynamic architectures. It introduces analysis techniques for a user program written in a high-level language which are aimed at finding the minimal sizes of computers which may execute this program. Next, it considers techniques for assigning the DC group hardware resource among several concurrent programs, thus allowing one to increase the executional parallelism obtained on the same hardware equipment. The assignment techniques studied in the paper form a core of the assignment subsystem included into the operating system of dynamic architecture. It is shown that the presented methodology is simple and straightforward requiring no complex computations. As a result, the resource assignment among user programs can be performed quickly and efficiently.

This paper considers the synthesis of the network N which realizes the original program (problem oriented network) N is assembled from n unit modules partitioned into r categories (r ≥ 1) each of which is formed from identical modules.

This paper considers a state assignment which permits one to obtain two different realizations of a sequential machine (sm). First, as a result of this assignment we obtain a double shift-register realization of an sm by means of p pairs of shift-registers, each pair of registers having the same number of stages ai(i = 1,...,p). Such realizations are called multiple-variable-length-shift-register-realizations (MVL-SRR's). Second, this state assignment permits us to obtain multimodule type iterative realizations made by means of p different module types, each of them being copied aitimes (i = l,...,p). We call these realizations multiple-variable-length-iterative-realizations (MVL-IR's). Thus any MVL-SRR or MVL-IR is uniquely specified by γp, = (a1,...,ap,).