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Nishit Shah

dblp:94/3364 · DBLP profile ↗
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2ranked-venue papers
0as first author
1since 2021 · last 2023
—ORCID · unresolved

Domains — the database's venue-derived domains; a paper can count in several

Graphics, computer vision, multimedia, augmented reality and games · 1 · 1 since 2021Applied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Processor architecture and microarchitecture · 50% Cloud and datacenter computing · 50%
Computer networks
1 paper
Routing and switching · 77% Network performance modeling · 23%

Topics — the 3 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture › special-purpose processor
network processor
0.112006
Processor Scheduler for Multi-Service Routers · RTSS 2006
Cloud and datacenter computing › cluster resource management and scheduling › resource scheduling
service scheduling
0.112006
Processor Scheduler for Multi-Service Routers · RTSS 2006
Network performance modeling › delay analysis
packet delay
0.012006
Processor Scheduler for Multi-Service Routers · RTSS 2006

Methods — techniques the papers use, named apart from their topics

scheduling algorithm · 0.1prototype implementation · 0.1
YearPublicationVenuePosition
2023 ARUBA: An Architecture-Agnostic Balanced Loss for Aerial Object Detection
abstract
Deep neural networks tend to reciprocate the bias of their training dataset. In object detection, the bias exists in the form of various imbalances such as class, background-foreground, and object size. In this paper, we denote size of an object as the number of pixels it covers in an image and size imbalance as the over-representation of certain sizes of objects in a dataset. We aim to address the problem of size imbalance in drone-based aerial image datasets. Existing methods for solving size imbalance are based on architectural changes that utilize multiple scales of images or feature maps for detecting objects of different sizes. We, on the other hand, propose a novel ARchitectUre-agnostic BAlanced Loss (ARUBA) that can be applied as a plugin on top of any object detection model. It follows a neighborhood-driven approach inspired by the ordinality of object size. We evaluate the effectiveness of our approach through comprehensive experiments on aerial datasets such as HRSC2016, DOTAv1.0, DOTAv1.5 and VisDrone and obtain consistent improvement in performance.
Rebbapragada V. C. Sairam, Monish Keswani, Uttaran Sinha, Nishit Shah, Vineeth N. Balasubramanian
WACV4
2006 Processor Scheduler for Multi-Service Routers
abstract
In this paper, we describe the design and evaluation of a scheduler (referred to as Everest) for allocating processors to services in high performance, multi-service routers. A scheduler for such routers is required to maximize the number of packets processed within a given delay tolerance, while isolating the performance of services from each other. The design of such a scheduler is novel and challenging because of three domain-specific characteristics: (1) difficult-to-predict and high packet arrival rates, (2) small delay tolerances of packets, and (3) significant overheads for switching allocation of processors from one service to another. These characteristics require that the scheduler be agile and wary simultaneously. Whereas agility enables the scheduler to react quickly to fluctuations in packet arrival rates, wariness prevents the scheduler from wasting computational resources in unnecessary context switches. We demonstrate that by balancing agility and wariness, Everest, as compared to conventional schedulers, reduces by more than an order of magnitude the average delay and the percentage of packets that experience delays greater than their tolerance. We describe a prototype implementation of Everest on Intel's IXP2400 network processor
Ravi Kokku, Upendra Shevade, Nishit Shah, Ajay Mahimkar, Taewon Cho, Harrick M. Vin
RTSS3