Prior research has developed an approach called Analog Mixed-signal Parameter Search Engine (AMPSE) [1] to reduce the cost of design of analog/mixed-signal (AMS) circuits. In this paper, we propose an adaptive sampling method (AS) to identify a range of Pareto-optimal versions of a given AMS circuit with different combinations of metric values to enable parameter-search based methods like AMPSE to efficiently serve multiple users with diverse requirements. As AMS circuit simulation has high run-time complexity, our method uses a surrogate model to estimate the values of metrics for the circuit, given the values of its parameters. In each iteration, we use a mix of uniform and adaptive sampling to identify parameter value combinations, use the surrogate model to identify a subset of these samples to simulate, and use the simulation results to retrain the model. Our method is more effective and has lower complexity compared with prior methods [2]–[4] because it works with any surrogate model, uses a low-complexity yet effective strategy to identify samples for simulation, and uses an adaptive annealing strategy to balance exploration vs. exploitation. Experimental results demonstrate that, at lower complexity, our method discovers better Pareto-optimal designs compared to prior methods. The benefits of our method, relative to prior methods, increase as we move from AMS circuits with low simulation complexities to those with higher simulation complexities. For an AMS circuit with very high simulation complexity, our method identifies designs that are superior to the version of the circuit optimized by experienced designers.

Analog mixed-signal (AMS) circuit architecture has evolved towards more digital friendly due to technology scaling and demand for higher flexibility/reconfigurability. Mean-while, the design complexity and cost of AMS circuits has substantially increased due to the necessity of optimizing the circuit sizing, layout, and verification of a complex AMS circuit. On the other hand, machine learning (ML) algorithms have been under exponential growth over the past decade and actively exploited by the electronic design automation (EDA) community. This paper will identify the opportunities and challenges brought about by this trend and overview several emerging AMS design methodologies that are enabled by the recent evolution of AMS circuit architectures and machine learning algorithms. Specifically, we will focus on using neural-network-based surrogate models to expedite the circuit design parameter search and layout iterations. Lastly, we will demonstrate the rapid synthesis of several AMS circuit examples from specification to silicon prototype, with significantly reduced human intervention.

A digital finite impulse response (FIR) filter design is fully synthesizable, thanks to the mature CAD support of digital circuitry. On the contrary, analog mixed-signal (AMS) filter design is mostly a manual process, including architecture selection, schematic design, and layout. This work presents a systematic design methodology to automate AMS FIR filter design using a time approximation architecture without any tunable passive component, such as switched capacitor or resistor. It not only enhances the flexibility of the filter but also facilitates design automation with reduced analog complexity. The proposed design flow features a hybrid approximation scheme that automatically optimize the filter's impulse response in light of time quantization effects, which shows significant performance improvement with minimum designer's efforts in the loop. Additionally, a layout-aware regression model based on an artificial neural network (ANN), in combination with gradient-based search algorithm, is used to automate and expedite the filter design. With the proposed framework, we demonstrate rapid synthesis of AMS FIR filters in 65nm process from specification to layout.

Stochastic time-to-digital converters (STDCs) are gaining increasing interest in submicron CMOS analog/mixed-signal design for their superior tolerance to nonlinear quantization levels. However, the large number of required delay units and time comparators for conventional STDC operation incurs excessive implementation costs. This paper presents a fully synthesizable STDC architecture based on an integral non-linearity (INL) scrambling technique, allowing order-of-magnitude cost reduction. The proposed technique randomizes and averages the STDC INL using a digital-to-time converter. Moreover, we propose an associated design automation flow and demonstrate an STDC design in 12nm FinFET process. Post-layout simulations show significant linearity and area/power efficiency improvements compared to prior arts.

Among different types of regression methods to model Analog/Mixed-Signal (AMS) circuits, the Artificial Neural Network (ANN) is a promising candidate due to its reasonable accuracy and fast evaluation. However, for complex AMS circuits with wide specification ranges, creating an ANN model requires a large training dataset. To reduce the required training dataset’s volume, we have proposed a circuit-connectivity-inspired ANN (CCI-NN), including multiple sub-ANNs linked according to the actual circuit connections. For validation, we have employed CCI-NN to model a three-stage amplifier and a current-steering digital-to-analog converter. For a certain modeling accuracy, the training dataset requirement is reduced by 3.5x-7.6x.

We propose a complete analog mixed-signal circuit design flow from specification to silicon with minimum human-in-the-loop interaction, and verify the flow in a 12nm FinFET CMOS process. The flow consists of three key elements: neural network (NN) modeling of the parameterized circuit component, a search algorithm based on NN models to determine its sizing, and layout automation. To reduce the required training data for NN model creation, we utilize transfer learning to improve the NN accuracy from a relatively small amount of post-layout/silicon data. To prove the concept, we use a voltage-controlled oscillator (VCO) as a test vehicle and demonstrate that our design methodology can accurately model the circuit and generate designs with a wide range of specifications. We show that circuit sizing based on the transfer learned NN model from silicon measurement data yields the most accurate results.

Analog and mixed-signal (AMS) computer-aided design tools are of increasing interest owing to demand for the wide range of AMS circuit specifications in the modern system on a chip and faster time to market requirement. Traditionally, to accelerate the design process, the AMS system is decomposed into smaller components (called modules ) such that the complexity and evaluation of each module are more manageable. However, this decomposition poses an interface problem, where the module’s input-output states deviate from when combined to construct the AMS system, and thus degrades the system expected performance. In this article, we develop a tool module-linking-graph assisted hybrid parameter search engine with neural networks (MOHSENN) to overcome these obstacles. We propose a module-linking-graph that enforces equality of the modules’ interfaces during the parameter search process and apply surrogate modeling of the AMS circuit via neural networks. Further, we propose a hybrid search consisting of a global optimization with fast neural network models and a local optimization with accurate SPICE models to expedite the parameter search process while maintaining the accuracy. To validate the effectiveness of the proposed approach, we apply MOHSENN to design a successive approximation register analog-to-digital converter in 65-nm CMOS technology. This demonstrated that the search time improves by a factor of 5 and 700 compared to conventional hierarchical and flat design approaches, respectively, with improved performance.

A traditional analog mixed-signal (AMS) design mostly relies on the designer's knowledge and can only afford exploring over a narrow design space due to expensive SPICE simulation. However, a neural network (NN)-based model of an AMS circuit potentially enables fast exploration of the design space thanks to its low computation cost. Unfortunately, to build an NN model with sufficient accuracy, a training dataset is needed, incurring SPICE simulations during different design phases. Therefore, it is prudent to train it with a larger dataset in an earlier design phase (e.g. schematic design) but a significantly reduced dataset in a later design phase (e.g. postlayout design or migration to more advanced technology node), as simulation cost increases sharply in later design phases. In this paper, we propose the use of transfer learning (TL) with Bayesian optimization-aided sampling (BOAS) to reduce the required size of training datasets for NN models in later design phases. To prove the concept, we show that 150X and 17X dataset reductions are possible for a digital-to-analog converter (DAC) in the post-layout design phase and an amplifier in the technology migration phase, respectively.

The design and verification of analog and mixed-signal (AMS) circuits typically involve many time-consuming simulations to qualify target specifications or optimize the design parameters for better performance. The long simulation time significantly slows down the speed of optimization iterations for both human designers and automatic AMS optimizers, inevitably resulting in high design costs and less-optimized designs. In this work, we propose a convolutional neural network (CNN)-based early performance assertion (CEPA) scheme to identify designs with unsatisfactory performance quickly and accurately. Thanks to the feature extraction capability of CNN, CEPA only requires a short duration of transient waveform to predict the satisfaction of the target specifications for a certain design that is otherwise obtained by a long transient simulation. In addition, applying the fine-tuning technique to the proposed CEPA scheme can further extend the inference from schematic-level simulation to post-layout simulation with only a few training samples (i.e., enhancing CEPA's usage with a low training cost). A sample-and-hold circuit and a delta-sigma digital-to-analog converter are presented to prove the effectiveness of the proposed CEPA scheme. With its maximum assertion accuracy of 99%, CEPA reduces the simulation time for assertion by orders of magnitude.

Integrated circuit design in the late CMOS era is challenged by the ever-increasing variability and reliability issues. The situation is further compounded by real-time uncertainties in workload and ambient conditions, which dynamically influence the degradation rate. To improve design predictability and guarantee system lifetime, accurate modeling, and simulation tools for reliability are essential to both digital and analog circuits. This paper presents cross-layer solutions for emerging reliability threats, including: 1) device-level modeling of reliability mechanisms, such as transistor aging and its statistical behavior; 2) circuit-level long-term aging models that capture unique operation patterns in digital and analog design, and directly predict the degradation; and 3) simulation methods for very-large-scale designs. Built on the long-term model, the new methods significantly enhance the accuracy and efficiency of reliability analysis. As validated by silicon data, these solutions close the gap between the underlying reliability physics and circuit/system design for resilience.

This work proposes a non-uniform sampling analog-to-digital converter (ADC) architecture that embeds an alias-free filter in the asynchronous digital domain to relax the requirements of the analog anti-aliasing filter, improve the overall signal dynamic range, and interface directly with synchronous digital circuitry. Both event-driven voltage and time quantizers are used in the conversion process. Furthermore, an analytical model for estimating their quantization noise power is derived, which matches the numerical simulation with less than 4% deviation within the region of interest. A signal to noise ratio (SNR) improvement of 27dB over conventional, uniformly sampled Nyquist ADCs is obtained given the same 10-bit quantizer.

Ultra-wideband (UWB) impulse radio is a promising technique for low-power bio-medical communication systems. While a range of analog and digital UWB architectures exist, the mostly-digital approach without analog down-conversion enables better technology scaling and signal processing flexibility. Furthermore, recently proposed sub-sampling schemes and advances in high-speed ADC circuit design are helping to make this approach more feasible at low power. However, architectures that directly sample the received signal are more vulnerable to sampling jitter. Currently, there does not exist a model describing the impact of sampling jitter making it difficult to determine appropriate tolerances or to establish the feasibility of digital architectures. To address this problem, we have developed a model of sampling jitter and derived a generic bit error rate expressions for a digital UWB modem with sampling jitter, additive noise, and imperfect channel estimation in a generic multipath environment. We then use this model to investigate the performance of sub-sampled digital UWB in a body area network. This paper explains this analytical model and compares it with simulations results for communication around the body.

This paper describes the digital complex signal processing techniques for a pulse-based UWB radio. The proposed baseband is essential to fully exploit the wideband signal characteristics as well as compensating the analog front-end impairments. The property and optimal usage of these signal processing blocks are analyzed for both data detection and precision ranging applications. The same signal processing approaches are applicable for baseband and passband UWB communications as both are of interest under FCC regulations.

This paper describes a signal processing technique which allows a reduction in the complexity of a transceiver for a 3.1-10.6 GHz ultra-wideband radio. The proposed system transmits passband pulses using a pulser and antenna, and the receiver front-end downconverts the signal frequency by subsampling, thus requiring substantially less hardware than a traditional narrowband approach. By exploring the properties of analytic signals, the system allows hardware reduction and a time resolution finer than the sampling period, which is useful for locationing or ranging applications.