Yoich Nagao

dblp:94/4454 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1975
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test › sequential circuit testing
checking experiments
0.011975
Easily Testable Sequential Machines with Extra Inputs · IEEE Trans. Computers 1975
Electronic design automation › hardware verification and test
design for testability
0.011975
Easily Testable Sequential Machines with Extra Inputs · IEEE Trans. Computers 1975
Electronic design automation
hardware verification and test
0.011975
Easily Testable Sequential Machines with Extra Inputs · IEEE Trans. Computers 1975
Electronic design automation › hardware verification and test
test generation
0.011975
Easily Testable Sequential Machines with Extra Inputs · IEEE Trans. Computers 1975

Methods — techniques the papers use, named apart from their topics

transfer sequence · 0.0extra input symbols · 0.0distinguishing sequence · 0.0
YearPublicationVenuePosition
1975 Easily Testable Sequential Machines with Extra Inputs
abstract
In this paper, an easily testable machine is defined as one which possesses: 1) a distinguishing sequence of length [log2 n] which forces the machine into a specific state S1, and 2) transfer sequences of length at most [1og2 n] to carry the machine from state S1 to state Si for all i. A design procedure is presented in which an arbitrary machine is augmented to an easily testable machine by adding two special input symbols to the original machine. An efficient procedure is also described for designing checking experiments for the easily testable machines. For an n-state, m-input symbol machine, this procedure gives a bound on the length of the checking experiment that is approximately mn[log2,n]. Furthermore, the total checking experiments are preset.
Hideo Fujiwara, Yoich Nagao, Tsutomu Sasao, Kozo Kinoshita
IEEE Trans. Computers2