This paper presents a compact, high-accuracy and scalable on-chip temperature sensor (TS) optimized for low-power embedded applications, such as system-on-chip (SoC) and microprocessor thermal monitoring. The proposed TS employs a capacitive-biased-diode (CBD) structure enhanced by an adaptive discharging period (ADP) technique to achieve high sensitivity and linearity without additional backend calibration. The CBD sensor output is digitized by an oversampling (OS) successive approximation register (SAR) ADC with custom vertical metal-oxide-metal (VMOM) capacitors and a mismatch error shaping (MES) technique, providing high accuracy in a minimized chip area. Additionally, a discharging clock chopping (DCC) technique is proposed to effectively suppresses low-frequency noise with minimal switch noise, while clock boosters are implemented to decrease the ON-resistance of switches, reducing nonlinearity effects. Fabricated in a standard CMOS 180nm process, the sensor occupies only 0.0251 mm2and consumes$3.6~\mu $W. It achieves a one-point trimmed inaccuracy of ±0.25°C over a temperature range of −40°C to 125°C.

Wake-up receivers (WuRXs) help to cut down the average power consumed by the wireless devices in the Internet of things (IoT). Compared to the non-standard designs, the standard (e.g. BLE-compliant) WuRX chips can be integrated seamlessly into the widely-deployed infrastructures, while there are more design challenges since the BLE-compliant WuRX should be resilient to adjacent-channel interferes as well as realize a high sensitivity. In traditional BLE-compliant WuRXs, the interferes were suppressed by an FBAR filter or a low-noise local oscillator (LO) generator, with the penalty of sensitivity degradation or additional power consumption. The existing edge-combine LO generating method can cut down the power consumption, while the increased LO noise significantly degraded the signal-to-interference ratio (SIR) performance. In this work, we have demonstrated a BLE-compliant WuRX chip that improves both the SIR and sensitivity with low power dissipation. Instead of the conventional I/Q path with 90 degrees out of the phase, a pseudo-I/Q dual-downconversion structure is proposed to offer a WuRX driven by 120-degree-apart ultra-low-power LOs signals, which helps to improve the SIR performance due to the lower LO noise than the conventional edge-combine methods. In addition, a dummy down-converter based mismatch-cancellation technique is proposed to improve the image rejection ratio (IRR) and sensitivity. Fabricated by a 65nm CMOS process, the proposed BLE-compliant WuRX chip achieves -21dB SIR in the adjacent channel as well as -94dBm sensitivity at the cost of only$306\mu $W power.

Radio frequency (RF) power-harvesting technology is widely used by the temperature sensors inside high-voltage power-distribution cabinets, which avoids the safety risks caused by the use of batteries. Although the RF electromagnetic wave generated by high-voltage electric fields inside the cabinet can serve as the power supply, it suffers from unstable energy density. As a result, an external device is usually required to power up and read the temperature sensor, such as the near-field communication (NFC) reader of a smartphone. In this case, the RF harvester of the temperature sensor should be sensitive enough to enable a safe operating distance between the external reader and cabinet. Traditional methods combined an AC-DC rectifier and a DC-DC converter to provide a sufficient-high supply voltage for the sensing circuits, but the sensitivity was limited to −21dBm. In this work, an oscillator-enhanced energy-fusion power-harvesting technique is proposed to extend the power-transfer range of NFC. The harvester picks up the NFC energy to start up an oscillator, which enhances the power-harvesting sensitivity of other RF electromagnetic waves such as the 433MHz component in the cabinet. Then, the harvested DC voltage can be increased due to the power superposition of both the 13.56MHz and 433MHz tones. The proposed technique is implemented in a power-harvesting chipset fabricated in 55nm CMOS and 65nm CMOS processes. Measurement results show that the sensitivity of 433MHz power harvester is improved by 4.1dB due to the enhancement of the NFC excited oscillator, which also extends the NFC power-transfer range to 9cm.

Battery-free tags offer a power-efficient solution for the wireless connection in Internet of Things (IoT), where the backscatter communication that is compatible with widely-deployed protocols such as Bluetooth Low Energy (BLE) significantly reduces the hardware cost thanks to the seamless integration into the existing infrastructure. However, there are three main shortcomings in the existing battery-free BLE tags: 1)The tag-to-access point (AP, uplink) communication ranges are limited to 97 meters at -10dBm incident power, which are not long enough for some outdoor scenes. 2) The AP-to-tag (downlink) communication in the state of the arts has not exceeded a 1Mbps data rate and a 4m range, disabling remote tag configuration. 3)The tag-to-tag communication has not been realized in a battery-free way, which cannot construct a passive IoT network. In this work, we demonstrate an integrated bidirectional passive BLE chip that conducts battery-free BLE communication in tag-to-tablet/smartphone, tablet/smartphone-to-tag, and tag-to-tag modes. The chip is implemented in a 65nm CMOS process. An all-digital intermediate frequency (IF) shaping technique is proposed to extend the tag-to-tablet/smartphone (uplink) communication range to 160m at$7.16\mu $W power consumption and a -10dBm incident tone. In addition, a$2^{nd}$-order intermodulation (IM2) based charge-domain GFSK demodulation technique is proposed to enable 1Mbps 12m downlink communication at$6.8\mu $W power consumption, which realizes both tablet/smartphone-to-tag and tag-to-tag communication in a fully battery-free way. As a result, the bidirectional passive BLE chip offers a potential solution for future battery-free IoT mesh network.

On-chip oscillators are suitable for low-cost and compact IoT applications, but their temperature stability is relatively poor. This paper presents a temperature compensation technique to improve the stability of an on-chip digitally-controlled oscillator (DCO). The oscillation period of the DCO and the local temperature are simultaneously extracted by a capacitively-biased-diode sensor operating in a code-division-modulation manner. As the period and local temperature readouts are correlated, the proposed technique can achieve accurate temperature compensation despite of voltage variations. With a single-point trim, the proposed oscillator achieves a temperature stability of 18.4 ppm/°C and a voltage stability of 0.24%/V. It consumes a power consumption of 231 μW at an oscillation frequency of 20 MHz.

This paper reports an active-buffer-free type-I sampling phase-locked loop (S-PLL). We innovate a fully-passive sampling phase detector with passive-gain multiplication after the sampler, resulting in a stably-boosted PD gain and better linearity. Together with a transformer-based rich-harmonic shaping voltage-controlled oscillator, the proposed S-PLL at 3.78 GHz exhibits an integrated jitter of 39.6 fsRMS (1 kHz to 100 MHz), and the jitter-power figure-of-merit scores −260.2 dB. The reference (REF) spur is −70.96 dBc due to the embedded REF-feedthrough suppression technique.

This article presents a low-jitter and low-spur type-II sampling phase-locked loop (S-PLL). The innovative introduction of a differential parallel-series double-edge sampling phase detector (S-PD) achieves a high phase-detection gain and reduces the S-PLL in-band phase noise (PN). Incorporating a transformer-based harmonic-rich shaping voltage-controlled oscillator (VCO), the proposed S-PLL prototyped in a 65-nm CMOS, operates at 3.6 GHz and scores an integrated jitter of 43.1 fsrms integrated from 1 kHz to 100 MHz, it also exhibits a jitter-power figure-of-merit (FOM) of −258.7 dB. The measured reference (REF) spur is −80.34 dBc at$f_{\mathrm {REF}}$and −75.17 dBc at$2f_{\mathrm {REF}}$, respectively.

The peripheral oxygen saturation (SpO2) reflects the metabolic capacity of the human body, which can be used in assessing or screening symptoms such as pulmonary embolism. Photoplethysmography (PPG) is a common method for SpO2 monitoring, while it suffers from interferences such as ambient light scattering, reflections, and motion artifacts. These interferences significantly degrade the accuracy of SpO2 monitoring. Filtering techniques are widely used to suppress the interferences in PPG signals. However, conventional PPG filtering techniques use a fixed window, which is not able to handle interferences at different frequencies. In this paper, we propose a flexible-window filtering technique to suppress the interferences in SpO2 monitoring. To validate the proposed technique, we built a prototype to monitor the in-vivo SpO2 of the human body. Measurement results show that the proposed technique reduces the mean absolute percentage error (MAPE) of SpO2 by 46% compared to the conventional methods.

The size of wireless systems is required to be reduced in many applications, such as ultra-low-power sensor nodes and wearable/implantable devices, where battery and crystal are the two main bottlenecks in system miniaturization. In recent years, battery-free radios based on wireless power transfer (WPT) have shown great potential in miniature wireless systems, while a reliable on-chip clock without a crystal remains a design challenge. Conventional methods utilized the RF WPT tone as the reference for clock generation, but the high RF frequency leads to high power consumption. In comparison, using a lower WPT frequency results in an antenna with a larger size. In this work, the$2^{\mathrm{nd}}$-order inter-modulation (IM2) component of the two RF WPT tones is extracted to lock an on-chip oscillator, providing a low-jitter PVT-robust clock. In this way, the wireless systems can benefit from: 1) The clock recovery circuits operate at a low IM2 frequency, reducing the power consumption. 2) The WPT can be set to a high RF frequency to minimize the antenna. Fabricated in 65 nm CMOS process, the proposed crystal-less clock generator takes a small area of 0.023 mm2 in a wireless system chip. Measured results show −92 dBc/Hz@10 kHz phase noise and 6.8$\mu \text{W}$power.

This paper proposes a novel auto loss compensation (ALC) system to enable non-contact operations for capacitive coupled body channel communication (CC-BCC). The system employs a time-division compensation mismatch indicator (CMI) to continuously monitor the compensation error, and dynamically adjust the compensation inductor through a PI controller. With the close-loop topology, the proposed ALC system has three advantages: First, the path loss induced by non-contact status and backward coupling effect can be compensated simultaneously; Second, this system can dynamically attenuate the path losses, even when the channel characteristics vary with time; Third, this system has high robustness, which is insusceptible to channel variations; The simulation results show that the loss reduction of the proposed ALC system is 18 dB higher than the conventional compensation technique in the worst case.

Body channel communication (BCC) is one of the best candidates for communications in wireless body sensor networks as it uses the human body as transmission media to minimize transmission loss resulting better energy efficiency. The main issue of BCC is the loss in its backward path, which is formed by the capacitive coupling between two floated GND electrodes (GEs) of transmitter (TX) and receiver (RX). To mitigate the backward path loss, an off-chip inductor could be used to resonate with the backward capacitance to reduce the impedance of the backward path. However, this method is not suitable for wearable applications as the off-chip inductor only works for fixed communication distance. In this paper, we present a novel self-adaptive capacitive compensation (SACC) scheme to reduce the capacitive loss of the backward path. The proposed system automatically estimates the distance between GEs of TX and RX with the help of received signal strength indicator (RSSI). The backward capacitance is then calculated based on the estimated distance. And then the capacitance is compensated by a digitally controlled active inductor to reduce the backward path loss. Simulation shows that the proposed scheme achieves more than 15 dB channel enhancement at the IEEE 802.15.6 standard frequency.

Human body communication (HBC) has significant advantage over wireless communication schemes in wireless body area networks (WBANs) in terms of power efficiency due to the high conductivity of human body. An accurate circuit model for transmission channel is necessary for optimizing the HBC transceiver performance. Conventional models achieve limited accuracy because of incomplete body tissue model or the use of tranmission-line at circuit level. In this paper, we proposed a comprehensive HBC circuit model which is based on 5 human-surface tissue layers representing the physiological characteristics of living tissues and the frequency dependence of their dielectric properties. Instead of using transmission-line, our model is based on lumped-element analysis, which is more accurate at the 21 MHz frequency band specified by the IEEE 802.15.6 HBC standard. We verified the proposed model by actual measurement on human body at various of communication distances. Experimental results show that the proposed model achieved the minimum error among all the modeling works, i.e., 1.80% minimum error and 2.24% maximal error at various communication distances.

Behavioral models are necessary to shorten the design turn-around time of phase-locked loops (PLLs). For general cases in a system-on-chip, the PLL can resist the supply noise from other modules by a low-dropout regulator. Therefore, interactions among the supply ports of PLL submodules play a much more important part in the overall noise performance. In this brief, we propose a time-domain charge-pump PLL model including supply-noise interactions inside PLL. Described by Verilog-A, the behavioral results are compared with the simulated results of transistor circuits. It can be seen that the proposed model has reduced the simulation time to about 1.7% when compared with transistor-level simulating by SpectreRF. Under a nonideal power grid, our model can improve the jitter simulation accuracy when compared with the conventional model, e.g., simulated jitter error is lowered by 52.6% under a power grid with 8-Ω power-line segment and 1-pF decoupling capacitance.

Body channel communication (BCC) is a most power efficient way for communications among sensors in a wireless body-area network (WBAN). In BCC, the forward signal of the quasi-static field is conducted by the body surface, whereas the backward path is formed by the electrostatic coupling between the GND electrodes (GEs) of transmitter and receiver. As a result, the transmission loss is dominated by the backward path, which has high impedance due to small air capacitance between two compact GEs. Conventional backward path enhancement techniques make use of a large inductor to resonate with the air capacitance in order to reduce the impedance. Such approach is not suitable for integrated solution and not reconfigurable for varying communication distances. In this paper, we propose a novel active channel enhancer to compensate the loss in backward path, which is integratable and reconfigurable for variable distances and frequencies. Designed with 0.13 µm CMOS process, the proposed active enhancer improves the quasi-static coupling by more than 15 dB for a wide frequency band of 40 MHz–120 MHz compared to the 4 dB enhancement of conventional method; and the power consumption is only 0.6 mW.

This paper presents an all-digital Gaussian frequency shift keying (GFSK) demodulator with robust clock data recovery (CDR) for low-intermediate-frequency (low-IF) receivers in wireless sensor networks (WSN). The proposed demodulator can detect and adapt to the intermediate frequency of the received signal automatically. In addition, the CDR can tolerate the frequency deviation of the input clock. An implementation of the demodulator with CDR is realized with HJTC 0.18 ¼m CMOS technology. The chip is designed for GFSK signals with a center frequency of 200 kHz, a modulation index of 1 and a data rate of 100 kbps. Experimental results show that the chip consumes 0.53 mA from a 1.8 V power supply, and only a 11 dB input signal to noise ratio (SNR) is required for 10-3 bit error rate (BER). The tolerance range for IF offset is \pm12.5% at 11 dB input SNR, and the CDR can tolerate frequency deviation of the input clock of \pm0.1%.

For the node chips of wireless sensor networks (WSN), low power and fast settling are the two most important factors. In this paper, a low-power fast-settling phase-locked loop (PLL) frequency synthesizer working at 1.72 GHz∼1.74 GHz is designed for a 100 kb/s gauss frequency shift keying (GFSK) WSN transceiver. Low power consumption is realized by a bond-wire voltage-controlled oscillator (VCO) and a multi-stage power-scaling prescaler. Instead of conventional diode-based electro-static discharge (ESD) protection, resistor-based ESD protection is proposed for the bond-wire VCO to decrease the parasitic capacitance so that the automatic frequency calibration (AFC) range is enlarged by 50%. In addition, a dynamic-bandwidth scheme is proposed to meet the requirements of time-division half-duplex WSN systems. The chip is implemented with HJTC 0.18 µm CMOS technology. Measured results show that the PLL consumes 10.6 mW and settles within 18 µs including the AFC process; the phase noise is −91.9 dBc/Hz@10 kHz and −119.3 dBc/Hz@1 MHz under the receiving (Rx) state, and −95.2 dBc/Hz@10 kHz and −116.8 dBc/Hz@1 MHz under the transmitting (Tx) state.