The advent of large-scale integration of logic circuits requires the definition of digital computer structure in terms of large functional arrays of logic of very few types. This paper describes a single-package arithmetic processor called the arithmetic building element (ABE). The ABE accepts operands in either conventional or signed-digit radix-r representation and produces signed-digit results, which the ABE can reconvert to conventional form. Radix 16 is chosen for illustrations. Arrays of ABE's may be arranged to implement unit- time parallel addition, all-combinational multiplication, and more complex functions which are presently computed by subroutines. To facilitate such arithmetic design, a graph model is developed which permits a translation of the given arithmetical algorithm into an interconnection diagram of ABE's. The design procedure is illustrated by an array for polynomial evaluation. Speed, cost, and roundoff error of the array are considered. A computer program has been written for the automatic translation of the algorithm graph to an interconnection graph, and for the evaluation of the cost and speed for a given polynomial degree and a given precision requirement.

To meet the challenge created by the advent of large- scale integration, a unique microelectronic arithmetic building element and combinational arithmetic nets, composed of the building elements, have been studied and proposed for arithmetic processor design. A fast division algorithm, particularly suitable for floating- point arithmetic, has also been developed for signed-digit arithmetic. This algorithm is characterized by the need of preprocessing the divisor and then exact generation of quotient digits. This paper describes the implementation of this division algorithm with the arithmetic building element and combinational arithmetic nets. The intention here is to explore the feasibility of applying large-scale integration technology to arithmetic processors.

The page-faulting rate is one of the important criteria measuring the performance of a virtual storage under demand paging. In a multiprogrammed and/or time-sharing environment, a job is not expected to be run from the beginning to the end without interruption. In effect, it is segmented into phases and run piecewise. When running in this "segmented mode," a job phase upon initiation will most likely not possess the storage contents left by its preceding job phase (from the same job). Further, a job running in a paging environment at time t has a nonzero probability of referencing information brought to the high-speed store before t. Hence, for a given job, the segmented mode will yield a higher page faulting rate than the "continuous mode" in which the job runs continuously from the beginning to the end. By saving and retrieving its "working ensemble" upon the termination and initiation of a job phase, a job can be made to possess an "apparent continuity" insofar as the storage activity is concerned. The performance of the "apparently continuous" mode is hoped to approximate that of the continuous mode with an insignificant amount of overhead. Based on this observation, a storage organization oriented toward the minimization of overhead, is proposed. Simulation has been done for verification.