Three new methods are presented for using linear models to generate confidence intervals for ADC nonlinearity. The methods are based on the servo loop method the tally and weight method and the code density method.

For very small-geometry devices, two-dimensional parasitic effects can be complicated and models with extracted parameters may not be sufficient for accurately analyzing circuit performance. Using a device-level simulator, PISCES-2B, with appropriate boundary conditions, the transient performance of an emitter coupled logic (ECL) inverter with collector-up bipolar transistors of 1 mu m*1 mu m has been analyzed. The propagation delay of this inverter is less than 30 ps for driving an output load of 2 fF with an output swing of 0.8 V at a biasing current of 120 mu A. The speed performance is the result of its buried common emitter structure and its very small collector-to-substrate parasitic capacitances.>

Quantities such as peak error and integral or differential nonlinearity are commonly used to characterize the performance of analog-to-digital converters. However, these measures are not readily applicable to converter architectures that use feedback and oversampling. An alternative set of parameters for characterizing the linear, nonlinear, and statistical properties of analog-to-digital (A/D) converters is suggested, and an algorithm, referred to as the sinusoidal minimum error method is proposed to estimate the values of these parameters. The suggested approach is equally suited to examining the performance of A/D converters by means or either computer simulations of experimental measurements on actual circuits.>

Oversampling and digital filtering have been used to design a per-channel voiceband codec with resolution that exceeds the typical transmission system requirement by more than 15 dB. This extended dynamic range will allow for the use of digital processing in the management of signal levels and system characteristics in many telecommunication applications. Digital filtering contained in the codec provides rejection of out-of-band inputs and smoothing of the analog output that is sufficient to eliminate the need for analog filtering in most telephone applications. Some analog filtering may be required only to maintain the expanded dynamic range in cases where there is a danger of large amounts of out-of-band energy on the analog input impairing the dynamic range of the modulator. The encoder portion of the oversampled codec comprises an interpolating modulator that samples at 256 kHz followed by digital filtering that produces a 16-bit PCM code at a sample rate of 8 kHz. In the decoder, digital processing is used to raise the sampling rate to 1 MHz prior to demodulation in a 17-level interpolating demodulator. The circuits in the codec are designed to be suitable for large-scale integration. Component matching tolerances required in the analog circuits are of the order of only ± 1 percent, While the digital circuits can be implemented with fewer than 5000 gates with delays on the order of 0.1 μs. In this paper the response of the codec is described mathematically and the results are confirmed by measurements of experimental breadboard models.

The technique of time-averaging interpolation provides a means for obtaining telephone quality digital-to-analog conversion using conventional digital integrated-circuit processing. This approach has been adopted in a monolithic circuit that decodes the 8-kHz companded PCM commonly used in voiceband communication systems. The circuit, realized in a standard buried collector bipolar technology, contains 300 integrated injection logic(I^{2}L)gates together with a current-driven resistive ladder network. The performance of the decoder exceeds typical toll network objectives.

A novel technique called interpolation has been used to integrate a per-channel PCM encoder in a standard digital circuit technology. This encoder converts voiceband analog signals to both an oversampled 1-bit code and uniform PCM with μ-law companding noise. The circuit comprises approximately 550 integrated injection logic gates together with a resistive digital-to-analog converter, a voltage reference, and a simple differential amplifier. The encoder is part of a full PCM codec chip set suitable for a broad range of voiceband telecommunication applications.

A differential current-switching circuit configuration is proposed for implementing threshold logic, and a first-order statistical analysis of the configuration is described. The configuration is intended for use within functional digital integrated circuits. It can be realized in a form that is fully compatible with conventional emitter-coupled logic (ECL).

This paper describes a companded analog-to-digital (A/D) converter for voiceband signals that is simple and potentially inexpensive. The converter uses only 18 coarsely spaced analog levels. Fine resolution is obtained by oscillating between these levels at an increased speed and averaging the result over a Nyquist interval. The companding used in the converter is effectively the same as that of μ-255 pulse-code modulation (PCM). In the encoding process a one-bit code is generated at 256 000 samples/s. This 1-bit per sample signal can be transmitted and decoded directly, or a simple digital circuit will produce a 13-bit, 8-kHz linear PCM signal that can be compressed to 8-bit companded PCM format. In this paper the basic operation of the 1-bit coder is described and its performance when connected to a 1-bit decoder is illustrated. Methods for obtaining both linear and compressed PCM are then presented, and the properties of these PCM signals with respect to noise, gain tracking, and harmonic content are described. Relative insensitivity to circuit component variations, absence of analog gates, along with the need to generate only a few analog levels, make the coder especially well suited to integrated circuit realization.

Multiplication is an essential operation in digital signalprocessing algorithms. In such applications the organization of a multiplier typically ranges from parallel array to serial-parallel pipeline, with many intermediate possibilities. In this concise paper, the parallel array and serial-parallel pipeline organizations are compared on the basis of the power dissipation needed to achieve a specified multiplication rate. The first-order comparison is intended to serve as a preliminary aid in the design of custom integrated multiplier circuits. The comparison illuminates the differences in circuit technology appropriate for the two organizations. It also indicates that, insofar as custom integrated circuit design is concerned, design parameters other than power dissipation are likely to be the dominant considerations in choosing a multiplier organization.

An algorithm for high-speed, two's complement, m-bit by n-bit parallel array multiplication is described. The two's complement multiplication is converted to an equivalent parallel array addition problem in which each partial product bit is the AND of a multiplier bit and a multiplicand bit, and the signs of all the partial product bits are positive.