The emergence of new applications in high-performance computing is driving the need for more efficient computing machines. As supercomputer architectures become increasingly complex, the combinatorial explosion of design spaces and the time-consuming nature of design simulations lead to challenging design space exploration problems. This work introduces an automated search framework to achieve power-performance-area efficient Arm Neoverse V1 processor designs. Based on multi-objective Bayesian optimization, we propose a new exploration algorithm named SEBO by enhancing the three main stages of the optimization. Experimental results show that SEBO can not only compete with the top state-of-the-art baseline algorithms, but also outperforms them in terms of the quality and diversity of the returned Pareto-optimal designs.

NET4EXA aims to develop a next-generation high-performance interconnect for HPC and AI systems, addressing the increasing demands of large-scale infrastructures, such as those required for training Large Language Models. Building upon the proven BXI (Bull eXascale Interconnect) European technology used in TOP15 supercomputers, NET4EXA will deliver the new BXI release, BXIv3, a complete hardware and software interconnect solution, including switch and network interface components. The project will integrate a fully functional pilot system at TRL 8, ready for deployment into upcoming exascale and post-exascale systems from 2025 onward. Leveraging prior research from European initiatives like RED-SEA, the previous achievements of consortium partners and over 20 years of expertise from BULL, NET4EXA also lays the groundwork for the future generation of BXI, BXIv4, providing analysis and preliminary design. The project will use a hybrid development and co-design approach, combining commercial switch technology with custom IP and FPGA-based NICs. Performances of NET4EXA BXIv3 interconnect will be evaluated using a broad portfolio of benchmarks, scientific scalable applications, and AI workloads.

Dear Euromicro Community, We are honored to serve as the general chairs for this year's Euromicro conference, which marks the 50th anniversary of this prestigious event. The joint 27th Digital Systems Design (DSD 2024) and the 50th Software Engineering and Advanced Applications (SEAA 2024) conferences will be held in Paris, the same city that hosted the first event, “Microprocessing and Microprogramming in Europe,” fifty years ago.

Integrated Circuits (IC) are increasingly present in our daily lives through various everyday objects. Many third-party companies are involved during their manufacturing process. It introduces many threats to the ICs' manufacturing, such as IP piracy and Hardware Trojans. Strong Logic Locking methodology is generally used to protect from IC piracy, such as counterfeiting or reverse engineering, and against Hardware Trojans insertion; however, the lack of automated tools fully integrated into a CAD flow limits the integration of countermeasures. This paper proposes mathematical models on the Strong Logic Locking method to optimize the security and an automatic security design inserted in an open CAD flow. We implemented an exact algorithm to maximize the security measure while implementing a strategy to minimize the impact of delay and area on the circuit. This algorithm is a custom branch and bound based on the mathematical model developed in this paper. In addition, we propose a strategy to limit the impact of countermeasures on the delay. Furthermore, our approach takes place inside a standard open CAD flow after logic synthesis to be as generic as possible. The experiments carried out that security can be added in a standard open CAD flow with a reasonable computation time and a limited impact on the circuit. Our security measure is more precise than the previous one, with a limited area overhead defined by a user. The increase of the critical path is less than 7% for large benches with a limit of 10% area overhead.

High-performance many-core processors have complex computing architectures with many design parameters related to different levels (CPU macro/micro-architecture, interconnect, memory, specific accelerators, etc.). Design Space Exploration (DSE) is key to tackle the challenges related to the design of such processors, especially in the early stages. This work introduces A-DECA, a highly modular DSE approach for automating the exploration of design parameters. A-DECA combines simulators, models, and exploration strategies to derive relevant objective estimations while preserving a reasonable execution time. Thus, it provides a full methodology enabling the exploration of the design space in an easy-to-use, automatic, and effective way. A-DECA is evaluated in the context of next-generation HPC processors with various applications. We combine simulation tools and analytical formulations to assess PPA (Performance, Power, and Area). Based on an efficient implementation of a multi-objective genetic algorithm for the exploration strategy, current results show a great reduction of design space optimization by around 30% compared to the initial population. A-DECA optimizes the objectives and automatically returns a set of configurations with different characteristics allowing the architect to choose the best design according to the application context.

Circuit prototyping on multi-FPGA (Field Programmable Gate Arrays) platforms is a widely used technique in the VLSI (Very-Large-Scale Integration) context.Due to the ever-increasing size of circuits, it is necessary to use partitioning algorithms to place them on multi-FPGA platforms.Existing partitioning algorithms focus on minimizing the cut size but do not consider the critical path length, which can be degraded when mapping long paths to multiple FPGAs.However, recent studies try to consider the degradation of the critical path and the target topology but these works still use cutting minimization algorithms.In this work, we propose a mathematical model as an integer program (IP) based on the Red-Black Hypergraph model that considers the minimization of the critical path degradation and the target topology.We compare our partitioning results with KHMETIS, a min-cut algorithm, and show a better critical path for many circuit instances.

Summary This paper presents an efficient algorithm with performance guarantee to solve task scheduling problem on hybrid platforms with energy constraint and communication delays. The underlying platform architecture in this work is composed of two types of resources, CPU and GPU, often called hybrid parallel multicore platforms. We focus on finding a generic approach to schedule applications presented by Directed Acyclic Graph (DAG), which minimizes the makespan by considering communication delays and respecting an energy constraint. A two‐phase algorithm is proposed with a performance guarantee of 6 compared with the optimal solution; the first phase consists in solving the assignment problem to find the type of processor assigned to execute the tasks (CPU or GPU) using a linear program. In the second phase, we calculate the start execution time of each task to generate a feasible schedule. Finally, we test our algorithm on a large number of instances. These tests demonstrate that the proposed algorithm achieves a close‐to‐optimal performance.

Summary Many of today's important applications of our everyday lives, eg, weather forecast, design of plane and car shapes, medical analysis, or search engine queries depend on massively parallel computer programs executed in data centers. A large amount of energy is used to power them, and it is of primary importance to compute more efficiently to sustain the increasing demand of computing power while keeping energy consumption reasonable. One promising research path in this domain is heterogeneous systems since specific computing resources (processors, accelerators, etc) are more adapted to efficiently execute parts of applications. Nevertheless, the exploitation of these platforms raises new challenges in terms of application management optimization. The aim of our work is to determine effective algorithms to exploit these heterogeneous platforms by finding appropriate application mapping and scheduling to optimize the execution time and energy consumption with respect to various constraints. To achieve this goal, there is a need of a detailed modeling of the applications and the underlying hardware to be able to find realistic solutions. In this paper, we propose such a model, provide two implementations with state‐of‐the‐art tools, and propose a fast greedy online resolution algorithm and preliminary mapping and scheduling numerical results.

While raising the level of abstraction in design methodologies is uniformly accepted as desirable, raising Design For Test of complex VLSI chips is still challenging for both analysis and implementation. Still, testing logic can be described at the RT-level, and inserting it before synthesis has many advantages, among which the ability to debug testability issues early in the design flow, and leveraging the optimization done by the synthesis tool. But inserting DFT logic such as a full-scantest logic before synthesis brings its own challenges: the earlier it is inserted in the flow, the harder it is to provide low-overhead insertion. In this work, we combine the use of a lightweight synthesis with graph models for inferring logical proximity information from the design, and then use classic approximation algorithms for the traveling salesman problem to determine the scan-stitching ordering. We show how this procedure allows the decrease of the cost of both scan analysis and implementation, by measuring total wire length on placed and routed benchmark designs, both academic and industrial.

The memory BIST insertion involves the simultaneous optimization of several conflicting and competing objectives such as test time and power consumption during the test execution procedure. In this paper, a new memory BIST methodology is proposed which optimizes area overhead, test power and test time. It exploits Genetic Algorithms to find a set of Pareto optimal solutions. Since the designer is given a set of trade-off solutions between the three criteria, thus he can choose the most suitable one for his memory testing needs. The proposed algorithm is rigorously tested using several industrial designs.

We present a methodology, based on genetic algorithms, that optimizes shared heterogeneous Memory BIST architectures with regards to area, testing peak power and test time.