In this paper, we evaluate the error criticality of radiation-induced errors on modern High-Performance Computing (HPC) accelerators (Intel Xeon Phi and NVIDIA K40) through a dedicated set of metrics. We show that, as long as imprecise computing is concerned, the simple mismatch detection is not sufficient to evaluate and compare the radiation sensitivity of HPC devices and algorithms. Our analysis quantifies and qualifies radiation effects on applications' output correlating the number of corrupted elements with their spatial locality. Also, we provide the mean relative error (dataset-wise) to evaluate radiation-induced error magnitude. We apply the selected metrics to experimental results obtained in various radiation test campaigns for a total of more than 400 hours of beam time per device. The amount of data we gathered allows us to evaluate the error criticality of a representative set of algorithms from HPC suites. Additionally, based on the characteristics of the tested algorithms, we draw generic reliability conclusions for broader classes of codes. We show that arithmetic operations are less critical for the K40, while Xeon Phi is more reliable when executing particles interactions solved through Finite Difference Methods. Finally, iterative stencil operations seem the most reliable on both architectures.

Oil and gas companies trust Reverse Time Migration (RTM), the most advanced seismic imaging technique, with crucial decisions on drilling investments. The economic value of the oil reserves that require RTM to be localized is in the order of 10^{13} dollars. But RTM requires vast computational power, which somewhat hindered its practical success. Although, accelerator-based architectures deliver enormous computational power, little attention has been devoted to assess the RTM implementations effort. The aim of this paper is to identify the major limitations imposed by different accelerators during RTM implementations, and potential bottlenecks regarding architecture features. Moreover, we suggest a wish list, that from our experience, should be included as features in the next generation of accelerators, to cope with the requirements of applications like RTM. We present an RTM algorithm mapping to the IBM Cell/B.E., NVIDIA Tesla and an FPGA platform modeled after the Convey HC-1. All three implementations outperform a traditional processor (Intel Harpertown) in terms of performance (10x), but at the cost of huge development effort, mainly due to immature development frameworks and lack of well-suited programming models. These results show that accelerators are well positioned platforms for this kind of workload. Due to the fact that our RTM implementation is based on an explicit high order finite difference scheme, some of the conclusions of this work can be extrapolated to applications with similar numerical scheme, for instance, magneto-hydrodynamics or atmospheric flow simulations.

The computation capacity of the workstations in an open laboratory is enough to execute not only the local workload but some distributed computation. Unfortunately, the local workload introduces much uncertainty into the predictability of the system, which hinders the applicability of the job scheduling strategies. In this work, we introduce an estimation engine into our job scheduling system, termed CISNE. This prediction capacity allows us guarantee some limits to the turnaround time of parallel jobs. With this aim, three different estimation methods have been proposed and implemented in the CISNE system: a simulation tool, a historical system and an integration of both (hybrid). In this framework, we have compared our proposals to representative estimation methods in the literature. Likewise, we have analyzed these estimation methods in relation to different scheduling policies. These results reveal that the hybrid method achieves the best performance due to the fact that it combines the flexibility of a simulator to represent such a dynamic system as a non-dedicated cluster together with the accuracy given by the historical information

It is already known that the learning process can be accelerated with the mixture of theoretical classes and experimental work. This paper describes an interesting experiment with that combination in the teaching of computer architecture for Ph.D. students in collaboration with a researcher in a real design investigation. As the work progressed, a simple cyclical methodology arose as reference for future works.