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Robert E. Canright

dblp:95/2053 · DBLP profile ↗
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2ranked-venue papers
2as first author
0since 2021 · last 1987
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Integrated circuit design · 41% Interconnection networks and networks-on-chip · 36% Electronic design automation · 23%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design › interconnect
high-speed signaling		 0.011987
Reflections of High Speed Signals Analyzed as a Delay in Timing for Clocked Logic · DAC 1987
Interconnection networks and networks-on-chip
high-speed interconnect		 0.011986
Simulating and controlling the effects of transmission line impedance mismatches · DAC 1986
Electronic design automation
timing analysis		 0.011987
Reflections of High Speed Signals Analyzed as a Delay in Timing for Clocked Logic · DAC 1987
Electronic design automation
signal integrity		 0.011986
Simulating and controlling the effects of transmission line impedance mismatches · DAC 1986

Methods — techniques the papers use, named apart from their topics

transmission line simulation · 0.0timing analysis · 0.0design equations · 0.0CAD · 0.0
YearPublicationVenuePosition
1987 Reflections of High Speed Signals Analyzed as a Delay in Timing for Clocked Logic
abstract
This paper develops equations that can extend the performance of high speed digital systems. The equations allow the application of timing analysis to the selection of the minimum series terminating resistor. Use of the minimum terminating resistor minimizes power dissipation and maximizes the drive capability of the terminated device. Detailed examples simplify the adaptation of these new design procedures to computer-aided design (CAD).
Robert E. Canright, A. R. Helland
 DAC1
1986 Simulating and controlling the effects of transmission line impedance mismatches
abstract
Convenient equations for simulating the effects of transmission line impedance mismatches are derived from basic theory. These equations prove useful in controlling the transient response of a transmission line. The simulation equation for the load voltage is used to create design equations. Acceptable impedance mismatches are demonstrated in the context of criteria for acceptable transient voltages on a high-speed interconnection.
Robert E. Canright
 DAC1