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Daeshik Lee

dblp:95/2478 · DBLP profile ↗
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6ranked-venue papers
2as first author
0since 2021 · last 1997
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 5 · 2 first-authorComputer networks · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
4 papers
Interconnection networks and networks-on-chip · 88% Processor architecture and microarchitecture · 12%
Computer networks
2 papers
Optical networks · 100%

Topics — the 11 heaviest of 13, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Optical networks › optical switching
optical time slot interchangers
0.021997
Optical TDM sorting networks for high-speed switching · IEEE Trans. Commun. 1997
Serial Array Time Slot Interchangers and Optical Implementations · IEEE Trans. Computers 1994
Optical networks
optical switching
0.011997
Optical TDM sorting networks for high-speed switching · IEEE Trans. Commun. 1997
Interconnection networks and networks-on-chip › switching network
multistage interconnection network
0.021994
Serial Array Time Slot Interchangers and Optical Implementations · IEEE Trans. Computers 1994
On the Augmented Data Manipulator Network in SIMD Environments · IEEE Trans. Computers 1988
Optical networks
optical interconnect
0.011994
Serial Array Time Slot Interchangers and Optical Implementations · IEEE Trans. Computers 1994
Interconnection networks and networks-on-chip
permutation network
0.011992
The Lambda Time Slot Permuter: A Bit-Controlled Time Slot Permuter · SC 1992
Interconnection networks and networks-on-chip › switching network
self-routing network
0.011992
The Lambda Time Slot Permuter: A Bit-Controlled Time Slot Permuter · SC 1992
Interconnection networks and networks-on-chip › permutation network
sort-banyan network
0.011997
Optical TDM sorting networks for high-speed switching · IEEE Trans. Commun. 1997
Interconnection networks and networks-on-chip
switching network
0.011997
Optical TDM sorting networks for high-speed switching · IEEE Trans. Commun. 1997
Interconnection networks and networks-on-chip › switching network › multistage interconnection network
augmented data manipulator network
0.011988
On the Augmented Data Manipulator Network in SIMD Environments · IEEE Trans. Computers 1988
Interconnection networks and networks-on-chip › routing algorithms
permutation routing
0.011988
On the Augmented Data Manipulator Network in SIMD Environments · IEEE Trans. Computers 1988
Processor architecture and microarchitecture
SIMD
0.011988
On the Augmented Data Manipulator Network in SIMD Environments · IEEE Trans. Computers 1988

Methods — techniques the papers use, named apart from their topics

space-time sorting · 0.0odd-even merge algorithm · 0.0space-to-time mapping · 0.0bitonic decomposition · 0.0spatial permutation network construction · 0.0cross-recurrence relations · 0.0
YearPublicationVenuePosition
1997 Optical TDM sorting networks for high-speed switching
abstract
The general time-space-time switching problem in telecommunications requires the use of multichannel time slot interchangers. We propose two multichannel time slot sorters which sort N/sup 2/ time-division multiplexed (TDM) optical inputs, arranged as N frames with N time slots per frame using O(Nlog/sup 2/N) optical switch elements. The TDM optical inputs are sorted in place without expanding the space-time fabric into a space-division switch. The hardware components used are 2/spl times/2 optical switches (LiNbO/sub 3/ directional couplers) and optical delay lines connected in a feedforward fashion. Two space-time variants of the spatial odd-even merge algorithm are used to design the sorters. By maintaining the number of shift-exchange operations invariant at each stage, the proposed sorters use fewer switches than previously proposed sorters using switches with feedback line delays. The use of local control at each 2/spl times/2 switch makes the proposed sorters more practical for high-speed optical inputs than Benes-based time slot permuters with global control and high latency, which affects interframe distance. Both time slot sorters support pipelining of input frames and sorted outputs are available at each time slot after an initial frame delay. The proposed sorters find practical application in the time-domain equivalents of space-division, nonblocking, self-routing packet switches using the sort-banyan architecture, such as the Starlite switch, Sunshine switch, etc.
Rajgopal Kannan, Daeshik Lee, Kyungsook Y. Lee, Harry F. Jordan
IEEE Trans. Commun.2
1994 Serial Array Time Slot Interchangers and Optical Implementations
abstract
We consider time slot interchangers (TSIs) which are built from 2/spl times/2 exchange switches and delays and which are useful for time division multiplexed (TDM) systems in telecommunications and pipelined systems such as time multiplexed optical multiprocessors. We formulate a general method for constructing TSIs based on multistage interconnection networks in the space domain via space-to-time mapping. Two types of TSIs, time slot permuters and time slot sorters, are considered. We review the time slot permuter based on the Benes network, and obtain the /spl Lambdaspl tilde/ time slot permuter based on the bit-controlled, self-routing /spl Lambda/ permutation network. The time slot sorter, S/sub N/, is obtained from the Batcher spatial sorting network. The generalized Lambda time slot permuter /spl Lambdasub Nsup q/ is obtained, in an algorithmic approach, by combining the idea of the /spl Lambdaspl tilde/ time slot permuter and Q-way bitonic decomposition (Q=2/sup q/). The numbers of switches, control complexities, and frame delays of these architectures are compared, and the problem of crosstalk in optical implementation is discussed. It is shown that control complexity can be traded against the number of switches.>
Harry F. Jordan, Daeshik Lee, Kyungsook Y. Lee, Srinivasan V. Ramanan
IEEE Trans. Computers2
1992 The Lambda Time Slot Permuter: A Bit-Controlled Time Slot Permuter
abstract
The authors formulated a general method for constructing time slot permuters from spatial permutation networks. Using the method, they constructed a new time slot permuter, the Lambda time-slot permuter. The Lambda time slot permuter is obtained from the bit-controlled, self-routing permutation network, the Lambda network. While the Lambda time slot permuter requires more hardware than the time slot permuter based on the Benes network described by S.V. Ramanan et al. (1990), its control is very simple. In the Lambda time slot permuter, a single bit from the destination tag in the first of a pair of time slots entering an exchange element is used as the control bit so that the switch setting can be done before the second time slot arrives; thus, it is possible that the switch setting does not incur any delay. The Lambda time slot permuter is suitable for a class of applications where on-the-fly control of the time slot permuter is important, and is especially efficient for a pipelined operation.>
Daeshik Lee, Kyungsook Y. Lee, Harry F. Jordan
SC1
1988 On the Augmented Data Manipulator Network in SIMD Environments
abstract
Formulas for the number of the augmented-data-manipulator (ADM)-passable permutations were given previously as cross-recurrence relations for the cardinalities of three specific subsets of such permutations. More concise, transparent recurrence formulas are derived utilizing a novel and conceptually simple model of the ADM. As a byproduct, a global control algorithm for the inverse ADM (IADM) is obtained that can set paths for all the IADM-passable permutations. This algorithm can be adapted for the ADM. Also included are two local control algorithms for the IADM/ADM: the signed bit difference tag control and the destination tag control.>
Kyungsook Y. Lee, Daeshik Lee
IEEE Trans. Computers2
1987 The Lambda Network: A New Permutation Network
Daeshik Lee
ICPP1
1986 Control Algorithms for the Augmented Data Manipulator Network
Kyungsook Y. Lee, Daeshik Lee
ICPP2