The advancement of deep submicrometer Integrated circuit manufacturing technology has pushed the use of embedded memory, and the strong demand of embedded nonvolatile memory for system-on-chip and system in package applications has made flash memory increasingly important as well. Nevertheless, the yield loss of memory products caused by deep submicrometer defects and manufacturing uncertainties is still a critical issue. In order to solve the yield issue, built-in self-repair (BISR) has been considered as the most cost-effective solution. However, implementing BISR on flash memories is not trivial. In this paper, we propose BISR schemes for nor flash memory and NAND flash memory, respectively. The BISR schemes perform built-in self-test, built-in redundancy analysis, and on-chip repair. For the BISR scheme of nor flash memory, a typical redundancy architecture is assumed, based on which we analyze three existing algorithms and propose a redundancy analysis (RA) algorithm. On the other hand, for NAND flash memory, an RA algorithm based on an efficient 2-D redundancy architecture is proposed, and considering the widely used page-mode operation in NAND flash memory, a method to discover currently accessed address is also proposed. A simulation tool is also developed, supporting nor flash memory and NAND flash memory. The simulation results show that our approach can effectively repair defective memories.

ECC has been widely used to enhance flash memory endurance and reliability. In this work, we propose an adaptive-rate ECC scheme with BCH codes that is implemented on the flash memory controller. With this scheme, flash memory can trade storage space for higher error correction capability to keep it usable even when there is a high noise level.

The strong demand of non-volatile memory for SOC and SIP applications has made flash memory increasingly important. However, deep submicron defects and process uncertainties are causing yield loss of memory products. To solve the yield issue, built-in self-repair (BISR) is widely believed to be cost effective. It is, however, non-trivial to implement BISR on flash memories. In this paper we propose a BISR scheme for NOR-type flash memory. The BISR scheme performs built-in self-test (BIST), built-in redundancy analysis (BIRA), as well as on-chip repair. A typical redundancy architecture for NOR-type flash memory is assumed, based on which we present a redundancy analysis (RA) algorithm. Experimental result shows that the proposed BISR scheme can effectively repair most defective memories.