Abstract We introduce Arches, a hardware simulation framework designed to explore and evaluate massively parallel ray‐tracing architectures. Operating at the cycle level, Arches captures detailed performance metrics, including computational throughput, on‐chip data movement across processors, caches, and off‐chip communication via an accurate memory system model. The framework is modular, allowing flexible configuration and interconnection of processor cores, caches, and custom hardware units, enabling easy exploration of diverse hardware architectures. Arches supports high‐performance parallel execution, simulating complex ray tracing workloads to image completion. It leverages the GNU toolchain, allowing users to write C++ software targeting both the simulated architecture and native execution for debugging, including support for custom instructions to control specialized hardware components. The framework provides comprehensive performance instrumentation, offering insights into time‐varying statistics across all modules and identifying performance bottlenecks. Our evaluations demonstrate that Arches delivers performance estimates closely matching real hardware, offering faster and more accurate simulations than existing open‐source hardware simulators. Its modularity also makes it a valuable tool for exploring alternative parallel computing strategies for high‐performance ray tracing, and its extensibility enables adaptation for other workloads or general‐purpose computation.

Data movement, particularly access to the main memory, has been the bottleneck of most computing problems. Ray tracing is no exception. We propose an unconventional solution that combines a ray ordering scheme that minimizes access to the scene data with a large on-chip buffer acting as near-compute storage that is spread over multiple chips. We demonstrate the effectiveness of our approach by introducing Mach-RT (Many chip - Ray Tracing), a new hardware architecture for accelerating ray tracing. Extending the concept of dual streaming, we optimize the main memory accesses to a level that allows the same memory system to service multiple processor chips at the same time. While a multiple chip solution might seem to imply increased energy consumption as well, because of the reduced memory traffic we are able to demonstrate, performance increases while maintaining reasonable energy usage compared to academic and commercial architectures. This article extends our previous work E. Vasiou, K. Shkurko, E. Brunvand, and C. Yuksel, "Mach-RT: A many chip architecture for high-performance ray tracing," in Proc. High-Perform. Graph. Conf., 2019 with design space exploration of the L3 cache size, more detailed evaluation of energy and memory performance, a discussion of energy delay product, and a brief exploration of boards with 16 chips. We also introduce new treelet enqueueing logic for the predictive scheduler.

Computer Science and Computer Engineering classes related to digital circuits, embedded systems, Human Computer Interaction (HCI), and a wide variety of "maker" subjects, would often like to include physical computing projects. Extending these physical computing ideas to physical realization of circuits is the next logical step, and has traditionally happened with low-cost non-soldered prototyping such as breadboards. However, many modern circuit components are now available only in tiny surface-mount technology (SMT) packages. Using these components essentially requires that students are able to design printed circuit boards (PCBs) specifically for their module. In this paper we describe an experience report of how we enhanced a student lab in a cost-effective way to enable students to develop, assemble, and solder custom PCBs that contain SMT components. This allows modern circuit components to be used, offers an enriched hands-on experience, and enables an expansion of the scope and complexity of student projects.

SimTRaX is a simulation infrastructure for simultaneous exploration of highly parallel accelerator architectures and how applications map to them. The infrastructure targets both cycle-accurate and functional simulation of architectures with thousands of simple cores that may share expensive computation and memory resources. A modified LLVM backend used to compile C++ programs for the simulated architecture allows the user to create custom instructions that access proposed special-purpose hardware and to debug and profile the applications being executed. The simulator models a full memory hierarchy including registers, local scratchpad RAM, shared caches, external memory channels, and DRAM main memory, leveraging the USIMM DRAM simulator to provide accurate dynamic latencies and power usage. SimTRaX provides a powerful and flexible infrastructure for exploring a class of extremely parallel architectures for parallel applications that are not easily simulated using existing simulators.

We introduce a new motion blur computation method for ray tracing that provides an analytical approximation of motion blurred visibility per ray. Rather than relying on timestamped rays and Monte Carlo sampling to resolve the motion blur, we associate a time interval with rays and directly evaluate when and where each ray intersects with animated object faces. Based on our simplifications, the volume swept by each animated face is represented using a triangulation of the surface of this volume. Thus, we can resolve motion blur through ray intersections with stationary triangles, and we can use any standard ray tracing acceleration structure without modifications to account for the time dimension. Rays are intersected with these triangles to analytically determine the time interval and positions of the intersections with the moving objects. Furthermore, we explain an adaptive strategy to efficiently shade the intersection intervals. As a result, we can produce noise-free motion blur for both primary and secondary rays. We also provide a general framework for emulating various camera shutter mechanisms and an artistic modification that amplifies the visibility of moving objects for emphasizing the motion in videos or static images.

We describe our experience designing and delivering a general education technological fluency course that frames the discussion of computer science and engineering technology (electronics and programming) in the context of sound-art: art that uses sound as its medium. This course is aimed at undergraduate students from a wide variety of backgrounds and is designed to fit into the ``Intellectual Explorations'' area of a general undergraduate program. The goal is to introduce computer engineering and computational principles to non-CS students through an exploration of sound-art, experimental and electronic music, noise-making circuits, hardware hacking, and circuit bending.

The growing do-it-yourself movement relies heavily on electronics, code, and data. Abundant resources and low cost materials result in people of all ages seeking to learn how to master these modern creative supplies. We will discuss how computer science educators might tap into teachable moments provided by this voluntary, informal, enthusiastic movement to promote formal computer science study. The success of introducing formal computer science skills in the context of computing as a creative tool has been well established in the areas of media computation and digital art. It is natural to extend this idea to computing as a tool for creating physical objects and for interacting with the physical world in different ways. This discussion will focus on examples of creative projects that expose topics in computer science, including microcontrollers, 3D printing, laser cutting, toy hacking, and environmental sensing. The session will emphasize the types of computer science concepts that naturally tie into each project. Attendees are encouraged to share their own project experiences and to reflect on lessons learned, accessibility of concepts, and practical issues of class management.

Are fine arts and technology compatible partners" Do these disciplines support each other or flinch when they are combined like oil and water" Do collaborative efforts provide interesting insights and opportunities for students" For practitioners" There seems to be an explosion of interest in exploring arts and technology connections: new media, digital media, kinetic art, new frontiers, emergent media, interdisciplinary, multidisciplinary, and transdisciplinary are only some of the terms used to describe this fusion of disciplines.

Abstract We propose two hardware mechanisms to decrease energy consumption on massively parallel graphics processors for ray tracing. First, we use a streaming data model and configure part of the L2 cache into a ray stream memory to enable efficient data processing through ray reordering. This increases L1 hit rates and reduces off‐chip memory energy substantially through better management of off‐chip memory access patterns. To evaluate this model, we augment our architectural simulator with a detailed memory system simulation that includes accurate control, timing and power models for memory controllers and off‐chip dynamic random‐access memory . These details change the results significantly over previous simulations that used a simpler model of off‐chip memory, indicating that this type of memory system simulation is important for realistic simulations that involve external memory. Secondly, we employ reconfigurable special‐purpose pipelines that are constructed dynamically under program control. These pipelines use shared execution units that can be configured to support the common compute kernels that are the foundation of the ray tracing algorithm. This reduces the overhead incurred by on‐chip memory and register accesses. These two synergistic features yield a ray tracing architecture that reduces energy by optimizing both on‐chip and off‐chip memory activity when compared to a more traditional approach.

This workshop introduces embedded programming and hardware using Arduino in a creative context to make machines that make drawings. This is a powerful way to introduce programming and physical computing concepts to students from high school to undergraduate and to students who might not normally be intrigued by a computing course. Participants experience this curriculum first hand by using breadboards and electronic components to create circuits that they control programmatically. Using the Arduino C-based software, participants modify and develop code to control light sensors, range finders, pressure sensors, and servos. Provided art materials turn the circuits into mesmerizing contraptions that draw. Laptop required. Arduino and electronic components provided during the workshop. Additional information and materials at www.buildingsteam.org

Bounding volume hierarchies (BVHs) are a popular acceleration structure choice for animated scenes rendered with ray tracing. This is due to the relative simplicity of refitting bounding volumes around moving geometry. However, the quality of such a refitted tree can degrade rapidly if objects in the scene deform or rearrange significantly as the animation progresses, resulting in dramatic increases in rendering times and a commensurate reduction in the frame rate. The BVH could be rebuilt on every frame, but this could take significant time. We present a method to efficiently extend refitting for animated scenes with tree rotations, a technique previously proposed for off-line improvement of BVH quality for static scenes. Tree rotations are local restructuring operations which can mitigate the effects that moving primitives have on BVH quality by rearranging nodes in the tree during each refit rather than triggering a full rebuild. The result is a fast, lightweight, incremental update algorithm that requires negligible memory, has minor update times, parallelizes easily, avoids significant degradation in tree quality or the need for rebuilding, and maintains fast rendering times. We show that our method approaches or exceeds the frame rates of other techniques and is consistently among the best options regardless of the animated scene.

The design of computer games can be a powerful motivator as students learn about computer architecture and design. Students in classes where computer designs are developed and implemented (usually on Field Programmable Gate Arrays (FPGAs)) seem much more highly motivated if their computer design can be used for something visual and interactive when the project is complete. However, ensuring that the student teams can have a working game by the end of a semester requires careful planning of how their computer designs will interact with the world. Keyboard inputs and VGA outputs are a relatively simple set of I/O interfaces that open up significant new potential for development of game applications on the student's own computer designs. In this paper we describe the curriculum of a computer design course that uses game design as a carrot to encourage active student exploration and deeper understanding of computer architecture, I/O subsystems, and computer implementation.

We describe a cross-disciplinary collaborative course that pairs computer science and engineering (CSE) students with art students to engage in joint engineering design and creative studio projects. These projects combine embedded system design with sculpture to create kinetic art. We believe that this is a natural pairing of two disparate disciplines, and one that provides distinct educational benefits to both groups of students. In this paper we describe the course content, the collaborative process, the materials used in the class, and experience with a pilot version of the course taught in Fall 2009 the University of Utah.

Ray tracing efficiently models complex illumination effects to improve visual realism in computer graphics. Typical modern GPUs use wide SIMD processing, and have achieved impressive performance for a variety of graphics processing including ray tracing. However, SIMD efficiency can be reduced due to the divergent branching and memory access patterns that are common in ray tracing codes. This paper explores an alternative approach using MIMD processing cores custom-designed for ray tracing. By relaxing the requirement that instruction paths be synchronized as in SIMD, caches and less frequently used area expensive functional units may be more effectively shared. Heavy resource sharing provides significant area savings while still maintaining a high MIMD issue rate from our numerous light-weight cores. This paper explores the design space of this architecture and compares performance to the best reported results for a GPU ray tracer and a parallel ray tracer using general purpose cores. We show an overall performance that is six to ten times higher in a similar die area.

In the past ten years, computer architecture has seen a paradigm shift from emphasizing single thread performance to energy efficient, throughput oriented, chip multiprocessors. Several studies have suggested that it may be worthwhile to off-load execution of the operating system (OS) to one or more of these cores, or reconfigure hardware during OS execution. To be effective, these techniques must balance the cost of off-loading or re-configuration, versus the potential benefits, which are typically unknown at decision time. These decision points are typically implemented by manually instrumenting a few OS routines (out of hundreds). Such a preliminary research effort cannot be sustained across several operating systems and hardware configurations. We argue that decisions made in software are often sub-optimal because they are expensive in terms of run-time overhead and because applications vary in their use of OS features. We propose that these decision mechanisms should be supported through a hardware based OS run-length predictor, that removes the onus from OS developers. Our final design results in a 95% prediction accuracy for OS intensive applications, while requiring only 2 KB of storage.

A synthetic noise function is a key component of most computer graphics rendering systems. This pseudo-random noise function is used to create a wide variety of natural looking textures that are applied to objects in the scene. To be useful, the generated noise should be repeatable while exhibiting no discernible periodicity, anisotropy, or aliasing. However, noise with these qualities is computationally expensive and results in a significant fraction of the run time for scenes with rich visual complexity. We propose modifications to the standard algorithm for computing synthetic noise that improve the visual quality of the noise, and a parallel hardware implementation of this improved noise function that allows the use of reduced precision arithmetic during the noise computation. The result is a special-purpose function unit for producing synthetic noise that computes high-quality noise values approximately two orders of magnitude faster than software techniques. The circuit, using a commercial CMOS cell library in a 65nm process, would run at 1GHz and consume 325μm x 325μm of chip area.

Threaded Ray eXecution (TRaX) is a highly parallel multithreaded multicore processor architecture designed for real-time ray tracing. The TRaX architecture consists of a set of thread processors that include commonly used functional units (FUs) for each thread and that share larger FUs through a programmable interconnect. The memory system takes advantage of the application's read-only access to the scene database and write-only access to the frame buffer output to provide efficient data delivery with a relatively simple memory system. One specific motivation behind TRaX is to accelerate single-ray performance instead of relying on ray packets in single-instruction-multiple-data mode to boost throughput, which can fail as packets become incoherent with respect to the objects in the scene database. In this paper, we describe the TRaX architecture and our performance results compared to other architectures used for ray tracing. Simulated results indicate that a multicore version of the TRaX architecture running at a modest speed of 500 MHz provides real-time ray-traced images for scenes of a complexity found in video games. We also measure performance as secondary rays become less coherent and find that TRaX exhibits only minor slowdown in this case while packet-based ray tracers show more significant slowdown.

Asynchronous microengines are an attractive alternative to globally synchronous systems for the realization of high performance programmable controllers. However, because of the specific demands of asynchronous signaling, it is not always easy to use existing standard cell libraries to implement asynchronous microengines. In this paper we present the design and evaluation of a CMOS cell set that augments a generic cell library with cells specific to the design of asynchronous microengines. These cells encapsulate behavior and timing information critical to the implementation of asynchronous microengine controllers. These special purpose cells result in higher performance circuits, and in a significant reduction in design time over a generic library. To validate the library, the control path of a popular asynchronous controller benchmark has been designed and fabricated through MOSIS.

Simulators for digital systems operate at a variety of levels of abstraction varying from detailed analog and switch level modeling of the transistor to cycle based descriptions of entire systems. We propose an even higher level simulator, called ARCS, based on the abstraction of an asynchronous communication event rather than of a clock cycle. Modeling systems at this level allows architectural level exploration of the design space before cycle-level details are available, and also allows the same framework to be used to refine architectural level simulations into more detailed simulations with increasingly fine grained notions of timing. The ARCS simulation framework uses concurrently operating threads in Java with communicating sequential processes (CSP) semantics as a natural expression of communication between concurrent hardware. To avoid synchronization bottlenecks ARCS models time using a communication driven clockwork model which allows for both user configurable runtime viewing of the simulation and post processing of complete simulation timing data.

We introduce a simple hierarchical design technique for using dynamic domino circuits to build high-performance self-timed data path circuits. We wrap the dynamic domino circuit in a wrapper that communicates using a request/acknowledge protocol and mediates the pre-charge/evaluate cycle of the dynamic logic. We apply standard bundled delay matching for completion detection but add an early completion feature that can signal completion if function validity can be determined from the output value. We call the resulting wrapper semi-bundled because of this early acknowledge. The circuit overhead required for this semibundled feature is relatively small, but can provide measurable speedup in some situations. The technique is suitable for any dynamic logic family that has a pre-charge/evaluate cycle, and that produces monotonic output transitions.

Asynchronous systems are being viewed as an increasingly viable alternative to purely synchronous systems. This paper gives an overview of the current state of the art in practical asynchronous circuit and system design in four areas: controllers, datapaths, processors, and the design of asynchronous/synchronous interfaces. 1 Asynchronous Control Classical asynchronous controllers were typically implemented as Huffman machines [67]. These machines do not use clocked latches or flip-flops: the state is simply stored on feedback loops. Typically a fundamental mode assumption is required, to insure correct operation: once an input change occurs, no new inputs may arrive until the machine has stabilized. Much of the basic theory on asynchronous state machines was developed by Huffman, Unger, and Mc-Cluskey (see [67]). Hazards, or the potential for glitches, are an important consideration in any asynchronous design [67]. In synchronous systems, the global clock usually filters out the effect of glitches. In asynchronous systems, there is no global clock, so any glitch may be interpreted as a valid signal change, and cause a malfunction. A number of techniques to eliminate combinational hazards, as well as critical races and essential hazards, have been proposed [67, 22, 5]. While this early work laid the foundations of asynchronous controller synthesis, the design methods had major limitations: (i) lack of ability to handle highly-concurrent environments; (ii) poor performance; (iii) problems in hazard elimination (in some methods); and (iv) lack of CAD optimization algorithms and tools. Since the early and mid 1980’s, several controller synthesis methods were developed, to address these limitations. These methods fall into three general categories: (i) state machines; (ii) Petri-net and graph-based methods; and (iii) translation methods. ___________________________

Impulse is a new memory system architecture that adds two important features to a traditional memory controller. First, Impulse supports application-specific optimizations through configurable physical address remapping. By remapping physical addresses, applications control how their data is accessed and cached, improving their cache and bus utilization. Second, Impulse supports prefetching at the memory controller, which can hide much of the latency of DRAM accesses. In this paper we describe the design of the Impulse architecture, and show how an Impulse memory system can be used to improve the performance of memory-bound programs. For the NAS conjugate gradient benchmark, Impulse improves performance by 67%. Because it requires no modification to processor, cache, or bus designs, Impulse can be adopted in conventional systems. In addition to scientific applications, we expect that Impulse will benefit regularly strided memory-bound applications of commercial importance, such as database and multimedia programs.

Most high-level synthesis tools for asynchronous circuits take descriptions in concurrent hardware description languages and generate networks of macromodules or handshake components. In this paper, we propose a peephole optimizer for these networks. Our peephole optimizer first deduces an equivalent blackbox behavior for the network using Dill's trace-theoretic parallel composition operator. It then applies a new procedure called burst-mode reduction to obtain burst-mode machines from the deduced behavior. In a significant number of examples, our optimizer achieves gate-count improvements by a factor of five, and speed (cycle-time) improvements by a factor of two. Burst-mode reduction can be applied to any macromodule network that is delay insensitive as well as deterministic. A significant number of asynchronous circuits, especially those generated by asynchronous high-level synthesis tools, fall into this class, thus making our procedure widely applicable.

Recent practical advances in asynchronous circuit and system design have resulted in renewed interest by circuit designers. Asynchronous systems are being viewed as an increasingly viable alternative to globally synchronous system organization. This tutorial will present the current state of the art in asynchronous circuit and system design in three different areas. The first section details asynchronous control systems. The second describes a variety of approaches to asynchronous datapaths. The third section is on asynchronous and self-timed circuits applied to the design of general purpose processors.

This paper presents a Design for Testability (DFT) tool called ACT (Asynchronous Circuit Testing) which uses a partial scan technique to make macro-module based self-timed circuits testable. The ACT tool is the first of its kind for testing macro-module based self-timed circuits. ACT modifies designs automatically to incorporate partial scan and provides a complete path from schematic capture to physical layout. It also has a test generation system to generate vectors for the testable design and to compute fault coverage of the generated tests. The test generation system includes a module for doing critical hazard free test generation using a new 6-valued algebra. ACT has been built around commercial tools from Viewlogic and Cascade. A Viewlogic schematic is used as the design entry point and Cascade tools are used for technology mapping.

We describe a technique to generate critical hazard-free tests for self-timed control circuits built using a macro-module library, in a partial scan based DFT environment. We propose a six-valued algebra to generate these tests which are guaranteed to be critical hazard free under an unbounded delay model. This algebra has been incorporated in a D-algorithm based automatic test pattern generator.

The problems with synchronous designs at high clock fre- quencies have been well documented. This makes an asynchronous ap- proach attractive for high speed technologies like GaAs. We investigate the issues involved by describing the design of a parallel multiplier that can be part of a floating point multiplier. We first present a new architecture called the partial army of array (PAA) that is more regular than a partial tree approach while having the same latency. We then show how this architecture can be used in a self-timed implementation in the style of micropipelines. We next describe how we can design the final carry propagate adder using a new precharged logic family in GaAs that we developed as part of this project. We conclude with some genera1 observations on doing asynchronous design in GaAs. Zndex Terms- Self-timed systems, micropipelines, multipliers, GaAs, precharged circuits.

In this paper, we present a methodology to perform fast testing of the control path of self-timed circuits. The speedup is achieved by testing all the execution paths in the control simultaneously. The circuits considered in this paper are those designed using an OCCAM based circuit compiler (1991). This Compiler translates an OCCAM program description into an interconnection of pre-existing self-timed macro-modules (1989, 1991). The method proposed involves modifying certain modules and structures in such a way that the circuits obtained by translation using these modified modules are testable in above mentioned way.

We describe a technique for translating semicustom VLSI circuits automatically into field programmable gate arrays (FPGAs) for rapid prototyping to develop a system. Using an array multiplier as an example of this translation, the VLSI circuits are designed using a cell-matrix based environment. The multiplier is implemented in CMOS in both synchronous and asynchronous pipelined versions, and translated into Actel FPGAs. All test chips were found to be fully functional, and the translation efficiency in terms of chip speed and area is shown.

Self-timed systems structured as multiple concurrent processes and communicating through self-timed queues are a convenient way to implement decoupled computer architectures. Machines of this type can exploit instruction level parallelism in a natural way, and can be easily modified and extended. However, providing a precise exception model for a self-timed micropipelined processor can be difficult, since the processor state does not change at uniformly discrete intervals. We present a precise exception method implemented for Fred, a self-timed, decoupled, pipelined computer architecture with out-of-order instruction completion.

This paper presents a partial scan method for testing control sections of macromodule based self-timed circuits for stuck-at faults. In comparison with other proposed test methods for self-timed circuits, this technique offers better fault coverage than methods using self-checking techniques, and requires fewer storage elements to be made scannable than full scan approaches with similar fault coverage. A new method is proposed to test the sequential network in this partial scan environment. Experimental data is presented to show that high fault coverage is possible using this method with only a subset of storage elements being made scannable.

Most high level synthesis tools for asynchronous circuits take descriptions in concurrent hardware description languages and generate networks of macromodules or handshake components. In this paper we describe a peephole optimizer for such macromodule networks that often effects area and/or time improvements. Our optimizer first deduces an equivalent black-box behavior for the given network of macromodules using Dill's trace-theoretic parallel composition operator. It then applies a new procedure called burst-mode reduction to obtain burst-mode machines, which can be synthesized into gate networks using available tools. Since burst-mode reduction can be applied to any macromodule network that is delay-insensitive as well as deterministic, our optimizer covers a significant number of asynchronous circuits, especially those generated by asynchronous high level synthesis tools.>

Asynchronous/self-timed circuits are beginning to attract renewed attention as a promising means of dealing with the complexity of modern VLSI designs. Very few analysis techniques or tools are available for estimating their performance. We adapt the theory of generalized timed Petri-nets (GTPN) for analyzing and comparing asynchronous circuits ranging from purely control-oriented circuits to those with data dependent control. Experiments with the GTPN analyzer are found to track the observed performance of actual asynchronous circuits, thereby offering empirical evidence towards the soundness of the modeling approach.>

In order to reasonably determine the correctness of asynchronous circuit implementations and specifications, Dill (1989) has developed a variant of trace theory. Trace theory describes the behavior of an asynchronous circuit by representing its possible executions as strings, called "traces." A useful relation defined in this theory is called conformance, which holds when one trace specification can be safely substituted for another. We propose a new relation in the context of Dill's trace theory, called strong conformance. We show that this relation is capable of detecting certain errors in asynchronous circuits that cannot be detected through conformance. Strong conformance also helps to justify circuit optimization rules where a component is replaced by another component having extra capabilities (e.g., it can accept more inputs). The structural operators of Dill's trace theory-compose, rename, and hide-are shown to be monotonic with respect to strong conformance. Experiments are presented using a modified version of Dill's trace theory verifier that implements a check for strong conformance.>

The authors explore one approach to self-timed design and describe implementations of an example circuit in three different technologies. The simple routing chip, used as the example has been described by writing a program in OCCAM, translated into a circuit consisting of a small set of basic modules, and implemented using Actel FPGA (field-programmable gate array), CMOS, and GaAs technologies. These technologies represent a wide range of price and performance characteristics.>

A method is presented for automatically translating a concurrent program into an asynchronous circuit. The translation procedure involves a simple syntax-directed translation from program constructs into initial asynchronous circuits. The resulting circuits are improved with correctness-preserving circuit-to-circuit transformations similar to peephole optimization in conventional compilers. Because these steps can be proved to be correct, the programmer is guaranteed that any specification met by the program will also be met by the circuit. A system has been constructed to perform the translation automatically. A brief description of the method is given, followed by two examples of programs translated into circuits.>