Demo Data from VLDB 2026 / reviewers in the wild / expert
Tzong-Yen Lin
dblp:95/3152
· DBLP profile ↗
6ranked-venue papers
2as first author
0since 2021 · last 2014
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Software engineering, system software, and programming languages
1 paper |
Compilers and program optimization · 56% Runtime systems and virtual machines · 44% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Runtime systems and virtual machines
binary translation |
0.1 | 1 | 2010 | DisIRer: Converting a retargetable compiler into a multiplatform binary translator · ACM Trans. Archit. Code Optim. 2010 |
Compilers and program optimization
intermediate representation |
0.1 | 1 | 2010 | DisIRer: Converting a retargetable compiler into a multiplatform binary translator · ACM Trans. Archit. Code Optim. 2010 |
Compilers and program optimization
code generation |
0.0 | 1 | 2010 | DisIRer: Converting a retargetable compiler into a multiplatform binary translator · ACM Trans. Archit. Code Optim. 2010 |
Methods — techniques the papers use, named apart from their topics
retargeting · 0.1disassembly · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2014 | Power-aware code scheduling assisted with power gating and DVS
Cheng-Yu Lee, Tzong-Yen Lin, Rong-Guey Chang |
Future Gener. Comput. Syst. | 2 |
| 2011 | Compiler Support for Concurrency Synchronization
Tzong-Yen Lin, Cheng-Yu Lee, Chia-Jung Chen, Rong-Guey Chang |
ICA3PP (1) | 1 |
| 2010 | DisIRer: Converting a retargetable compiler into a multiplatform binary translatorabstractThis article proposes an alternative yet effective way of constructing a multiplatform binary translator, by converting a retargetable compiler into a binary translator. The rationale is that a retargetable compiler usually parses source programs into an Intermediate Representation (IR), and then translates IR into object code of different targets after performing analysis and optimizations. Specifically, the mechanism of code generation for multiple platforms from IR is already in place, and the missing link of building a multiplatform binary translator is a tool to transform binary programs back into IR. In order to fill in this missing link, this article presents a tool, called thedisIRer. Just as a translator from machine language to assembly language is called a disassembler, a tool that translates executable binary programs to IR is called here a disIRer. The unique feature of this approach is that the retargetability of the binary translator is inherited directly from the retargetable compiler. A prototype multiplatform binary translator has been implemented upon GCC (the GNU Compiler Collection). DisIRer first converts binary programs back into GCC IR (Intermediate Representation), and afterward the GCC backend translates the IR to target binary programs of specified platforms. Experimental results show that x86 binary programs can be translated by this technique into ARM and Alpha binaries with reasonable code density and quality. Yuan-Shin Hwang, Tzong-Yen Lin, Rong-Guey Chang |
ACM Trans. Archit. Code Optim. | 2 |
| 2009 | Profile-based dynamic pipeline scaling
Kuan-Wei Cheng, Tzong-Yen Lin, Rong-Guey Chang |
J. Supercomput. | 2 |
| 2007 | Compiler Support for Dynamic Pipeline Scaling
Kuan-Wei Cheng, Tzong-Yen Lin, Rong-Guey Chang |
EUC | 2 |
| 2006 | Power-Aware Instruction Scheduling
Tzong-Yen Lin, Rong-Guey Chang |
EUC | 1 |