Virtual screening (VS) has become a key computational tool in early drug design and screening performance is of high relevance due to the large volume of data that must be processed to identify molecules with the sought activity-related pattern. At the same time, the hardware implementations of spiking neural networks (SNNs) arise as an emerging computing technique that can be applied to parallelize processes that normally present a high cost in terms of computing time and power. Consequently, SNN represents an attractive alternative to perform time-consuming processing tasks, such as VS. In this brief, we present a smart stochastic spiking neural architecture that implements the ultrafast shape recognition (USR) algorithm achieving two order of magnitude of speed improvement with respect to USR software implementations. The neural system is implemented in hardware using field-programmable gate arrays allowing a highly parallelized USR implementation. The results show that, due to the high parallelization of the system, millions of compounds can be checked in reasonable times. From these results, we can state that the proposed architecture arises as a feasible methodology to efficiently enhance time-consuming data-mining processes such as 3-D molecular similarity search.

In this work we show a study about which processes are related to chaotic and synchronized neural states based on the study of in-silico implementation of Stochastic Spiking Neural Networks (SSNN). Chaotic neural ensembles are excellent transmission and convolution systems. At the same time, synchronized cells (that can be understood as ordered states of the brain) are associated to more complex non-linear computations. We experimentally show that complex and quick pattern recognition processes arise when both synchronized and chaotic states are mixed. These measurements are in accordance with in-vivo observations related to the role of neural synchrony in pattern recognition and to the speed of the real biological process. The measurements obtained from the hardware implementation of different types of neural systems suggest that the brain processing can be governed by the superposition of these two complementary states with complementary functionalities (non-linear processing for synchronized states and information convolution and parallelization for chaotic).

The brain is characterized by performing many diverse processing tasks ranging from elaborate processes such as pattern recognition, memory or decision making to more simple functionalities such as linear filtering in image processing. Understanding the mechanisms by which the brain is able to produce such a different range of cortical operations remains a fundamental problem in neuroscience. Here we show a study about which processes are related to chaotic and synchronized states based on the study of in-silico implementation of Stochastic Spiking Neural Networks (SSNN). The measurements obtained reveal that chaotic neural ensembles are excellent transmission and convolution systems since mutual information between signals is minimized. At the same time, synchronized cells (that can be understood as ordered states of the brain) can be associated to more complex nonlinear computations. In this sense, we experimentally show that complex and quick pattern recognition processes arise when both synchronized and chaotic states are mixed. These measurements are in accordance with in vivo observations related to the role of neural synchrony in pattern recognition and to the speed of the real biological process. We also suggest that the high-level adaptive mechanisms of the brain that are the Hebbian and non-Hebbian learning rules can be understood as processes devoted to generate the appropriate clustering of both synchronized and chaotic ensembles. The measurements obtained from the hardware implementation of different types of neural systems suggest that the brain processing can be governed by the superposition of these two complementary states with complementary functionalities (nonlinear processing for synchronized states and information convolution and parallelization for chaotic).

This paper addresses a simple way for neural network hardware implementation based on probabilistic methodologies. We propose a new codification scheme that can be considered as an extension of stochastic computing (unipolar and bipolar codification formats), extending its representation range to any real number by using the ratio between two bipolar coded pulsed signals as codification method. Based on this codification, we propose the implementation of different linear and non-linear stochastic computational elements to be employed in artificial neural networks. Also this paper presents the accuracy associated to the proposed processing. The validation of the presented approach has been done with a sample application, (a spatial pattern classification example). The low cost in terms of hardware of the proposed methodology, along with the complexity of the mathematical expressions that can be implemented allows its use for massive parallel computing.

Spiking Neural Networks, the last generation of Artificial Neural Networks, are characterized by its bio-inspired nature and by a higher computational capacity with respect to other neural models. In real biological neurons, stochastic processes represent an important mechanism of neural behavior and are responsible of its special arithmetic capabilities. In this work we present a simple hardware implementation of spiking neurons that considers this probabilistic nature. The advantage of the proposed implementation is that it is fully digital and therefore can be massively implemented in Field Programmable Gate Arrays. The high computational capabilities of the proposed model are demonstrated by the study of both feed-forward and recurrent networks that are able to implement high-speed signal filtering and to solve complex systems of linear equations.

In this work we review the basic principles of stochastic logic and its application to the hardware implementation of Neural Networks. In this paper we show the mathematical basis of stochastic-based neurons along with the specific circuits that are needed to implement the processing of each neuron. We also propose a new methodology to reproduce the non-linear activation function. The proposed methodology can be used to implement any kind of Neural Network.

A new design of Spiking Neural Networks is proposed and fabricated using a 0.35 microm CMOS technology. The architecture is based on the use of both digital and analog circuitry. The digital circuitry is dedicated to the inter-neuron communication while the analog part implements the internal non-linear behavior associated to spiking neurons. The main advantages of the proposed system are the small area of integration with respect to digital solutions, its implementation using a standard CMOS process only and the reliability of the inter-neuron communication.

We present a pattern recognition methodology based on stochastic logic. The technique implements a parallel comparison of input data from a set of sensors to various pre-stored categories. Smart pulse-based stochastic-logic blocks are constructed to provide an efficient architecture that is able to implement Bayesian techniques, thus providing a low-cost solution in terms of gate count and power dissipation. The proposed architecture is applied to a specific navigation problem demonstrating that the system provides an almost optimal solution.

In this work we present an analytical formulation to estimate quickly and accurately the impact of crosstalk induced delay in submicron CMOS ICs gates taking into account time skew. Crosstalk delay is computed from the additional charge injected from the aggressor gate on the victim gate during simultaneous switching. The model provides a very good agreement with HSPICE simulations for a 0.18 mum technology

A chaotic IC is proposed and fabricated using a 0.35μm CMOS technology. The circuit iterates an N-shaped transfer function that can be modified using two external voltages, and is implemented using a three neurons network. The main advantages of the proposed circuit are based on its simplicity, small area (47 × 57μm2), and its MOS-only implementation requiring no more than 15 MOS transistors. Measurements show the suitability of the proposed system to reproduce a chaotic signal and to be used as a random number generator.

Delay testing at low- VDDhas been proposed as a useful test method to expose delay defects not detectable at nominal supply voltages. The advantage of this technique comes from the reduced transistor strength at lower supply voltages that increases the impact of delay defects in faulty circuits with respect to the fault-free population. The correlation between the supply voltage and the delay, founded on the well-known relationship between these two circuit parameters, is used to set the delay limit according to each supply voltage value. Less attention has been given to the impact of supply voltage reduction on the circuit parameter variation dependency and its impact on the delay distribution. In this work we investigate this relationship showing that for a 130nm technology the delay variations are worsened when lowering the supply voltage from the nominal 1.2V to 0.9V by more than 80%. This dependence may question the advantage of Low-VDDvs. delay testing for future nanometer technologies

In this paper we present a simple and efficient built-in temperature sensor for thermal monitoring of standard-cell based VLSI circuits. The proposed smart temperature sensor uses a ring-oscillator composed of complex gates instead of inverters to optimize their linearity. Simulation results from a 0.18-/spl mu/m CMOS technology show that the nonlinearity error of the sensor can be reduced when an adequate set of standard logic gates is selected.

As technology scales down, the static power is expected to become a significant fraction of the total power. The exponential dependence of static power with the operating temperature makes the thermal profile estimation of high-performance IC a key issue to compute the total power dissipated in the next-generation. In this paper we present accurate and compact analytical models to estimate the static power dissipation and the temperature of operation of CMOS gates. The models are the fundamentals of a performance estimation tool in which numerical procedures are avoided for any computation to set a faster estimation and optimization. The models developed are compared to measurements and SPICE simulations for a 0.12 /spl mu/m technology showing excellent results.

We present a compact, fully physical, analytical model for the propagation delay and the output transition time of deep-submicron CMOS gates. The model accounts for crosstalk effects, short-circuit currents, the input-output coupling capacitance and carrier velocity saturation effects. It is based on the nth-power law MOSFET model and computes the propagation delay from the charge delivered to the gate. Comparison with HSPICE simulations and other previously published models for different submicron technologies show significant improvements in terms of accuracy.

As chips become faster, the need to test them at their intended speed of operation has been recognized. High-speed operation, together with the higher switching activity typically induced during test, can result in a die-thermal distribution significantly different from that achieved during normal operation. Differences in thermal map distribution between normal- and test-mode operations give rise to a non-uniform impact on the relative path delay within logic blocks. The impact of test-induced hot spots may artificially slow down non-critical paths or speed-up critical ones with respect to the clock making the whole die to fail (pass) delay testing for a good (bad) part. The non-uniform thermal-induced delay is especially important for clock circuitry, the most critical block, which is impacted even if exact zero-skew clock routing algorithms are adopted. In this work we analyze the impact of thermal map temperature changes on the clock delay identifying a new delay-fault mechanism. We propose a technique to minimize the impact of different test- and normal-mode thermal maps by making the clock tree speed independent of temperature gradients. This technique allows applying confidently delay test patterns to the die regardless of the thermal-map test-induced modification.

The authors present an accurate analytical method for analyzing the power consumption in CMOS buffers. It is derived from the charge transferred through the circuit and makes use of the physically based MM9 MOSFET model (Velghe et al., 1994), (Foty et al., 1997) as well as a modified Sakurai alpha-power law model. The resulting analytical model accounts for the effects of input slew time, device sizes, carrier velocity saturation effects, input-to-output coupling capacitance, output load, and temperature. Results are compared to HSPICE simulations (level 50) and to other models previously published considering a large set of parameters for a 0.18 and 0.35 /spl mu/m technologies, showing significant improvements.

We present an accurate analytical expression to compute power and delay of domino CMOS circuits from a detailed description of internal capacitor switching and discharging currents. The expression obtained accounts for the main effects in complex sub-micron gates like velocity saturation effects, body effect, device sizes and coupling capacitors. The energy-delay product is also evaluated and analyzed. Results are compared to HSPICE simulations (level 50) for a 0.18 /spl mu/m CMOS technology.