Tokens are digital, transferable, and programmable assets and one of the most promising tools offered by blockchains. They could enable a wide range of applications, from down to earth to futuristic. One of the main issues in achieving wide adoption of tokens is onboarding: main platforms require users to deal with specific tools such as wallets, transaction fees, key generation, and storage. The most common solution to offer a familiar experience to naive users are custodial intermediaries, which have the important drawback of centralizing the process, and keeping users away from the advantages of self-sovereign assets control. In this paper, we present a process for the distribution of digital tokens to end users, exploiting “physical” objects for initial distribution. The process is aimed at making the onboarding of users not yet accustomed to blockchain tools and concepts as easy as possible, in a secure and decentralized way.

If on one hand the possibility of using pseudonymous identities is an important feature of blockchains and smart contracts, on the other hand official identity can be required in some applications to comply with regulations such as Know Your Customer and Anti Money Laundering. These regulatory compliance issues are usually dealt with either through “custo-dial” approaches, which however neutralize the decentralization of these systems, or with “whitelisting” mechanisms, that present critical issues with regard to privacy. In this paper we propose a protocol that allows only potentially identifiable users to use a given decentralized applications. The system ensures that users are identifiable only by a competent authority, under certain conditions, and that in any other case they remain pseudonyms. To evaluate performance and costs, we present an Ethereum implementation of the protocol.

Tokens are digital, transferable and programmable assets and one of the most promising tools offered by blockchains. They could enable a wide range of applications, from down to earth to futuristic. One of the main issues in achieving wide adoption of tokens is onboarding: main platforms require users to deal with specific tools such as wallets, transaction fees, key generation and storage.The most common solution to offer a familiar experience to naive users are custodial intermediaries, which have the important drawback of centralizing the process, and keeping users away from the intrinsic advantages of blockchains.In this paper we present a process for the distribution of digital tokens to end users, exploiting "physical" objects for initial distribution. The process is aimed at making onboarding of users not yet accustomed with blockchain tools and concepts maximally easy, in a secure and decentralized way.

Modern Building Management Systems (BMSs) have been designed to automate the behavior of complex buildings, but unfortunately they do not allow occupants to customize it according to their preferences, and only the facility manager is in charge of setting the building policies. To overcome this limitation, we present BuildingRules, a trigger-action programming-based system that aims to provide occupants of commercial buildings with the possibility of specifying the characteristics of their office environment through an intuitive interface. Trigger-action programming is intuitive to use and has been shown to be effective in meeting user requirements in home environments. To extend this intuitive interface to commercial buildings, an essential step is to manage the system scalability as large number of users will express their policies. BuildingRules has been designed to scale well for large commercial buildings as it automatically detects conflicts that occur among user specified policies and it supports intelligent grouping of rules to simplify the policies across large numbers of rooms. We ensure the conflict resolution is fast for a fluid user experience by using the Z3 SMT solver. BuildingRules backend is based on RESTful web services so it can connect to various BMSs and scale well with large number of buildings. We have tested our system with 23 users across 17 days in a virtual office building, and the results we have collected prove the effectiveness and the scalability of BuildingRules.

A large number of algorithms for multidimensional signals processing and scientific computation come in the form of iterative stencil loops (ISLs), whose data dependencies span across multiple iterations. Because of their complex inner structure, automatic hardware acceleration of such algorithms is traditionally considered as a difficult task. In this paper, we introduce an automatic design flow that identifies, in a wide family of bidimensional data processing algorithms, subportions that exhibit a kind of parallelism close to that of ISLs; these are mapped onto a space of highly optimized ad-hoc architectures, which is efficiently explored to identify the best implementations with respect to both area and throughput. Experimental results show that the proposed methodology generates circuits whose performance is comparable to that of manually optimized solutions, and orders of magnitude higher than those generated by commercial high-level synthesis tools.

The performance and the efficiency of recent computing platforms have been deeply influenced by the widespread adoption of hardware accelerators, such as graphics processing units (GPUs) or field-programmable gate arrays (FPGAs), which are often employed to support the tasks of general-purpose processors (GPPs). One of the main advantages of these accelerators over their sequential counterparts (GPPs) is their ability to perform massive parallel computation. However, to exploit this competitive edge, it is necessary to extract the parallelism from the target algorithm to be executed, which generally is a very challenging task. This concept is demonstrated, for instance, by the poor performance achieved on relevant multimedia algorithms, such as Chambolle, which is a well-known algorithm employed for the optical flow estimation. The implementations of this algorithm that can be found in the state of the art are generally based on GPUs but barely improve the performance that can be obtained with a powerful GPP. In this article, we propose a novel approach to extract the parallelism from computation-intensive multimedia algorithms, which includes an analysis of their dependency schema and an assessment of their data reuse. We then perform a thorough analysis of the Chambolle algorithm, providing a formal proof of its inner data dependencies and locality properties. Then, we exploit the considerations drawn from this analysis by proposing an architectural template that takes advantage of the fine-grained parallelism of FPGA devices. Moreover, since the proposed template can be instantiated with different parameters, we also propose a design metric, the expansion rate, to help the designer in the estimation of the efficiency and performance of the different instances, making it possible to select the right one before the implementation phase. We finally show, by means of experimental results, how the proposed analysis and parallelization approach leads to the design of efficient and high-performance FPGA-based implementations that are orders of magnitude faster than the state-of-the-art ones.

Smart buildings have been proposed as the solution for the creation of comfortable and energy-efficient living and working spaces. In the last few years, the energy-efficiency aspect is becoming more and more important and for this reason a lot of research effort has focused on the optimization of energy consumption, especially for what concerns commercial buildings, since they contribute to the 70% of the total energy consumption of an electrical grid. In addition, commercial buildings are usually already equipped with highly-instrumented distributed systems and infrastructures that simplify the creation of a smart environment. Nevertheless, we believe that also residential buildings should be taken into account, since their energy consumption is not negligible (they account for the remaining 30%) and the flexibility of their occupants in the usage of appliances (generally much higher than the ones of commercial buildings) could be better exploited. Within this context, we analyze the hardware infrastructure, intended as the network of sensors, actuators, appliances and accumulators, of this kind of buildings. Moreover, we discuss which kind of networking infrastructures is needed in order to cope with the particularities of complex residential buildings. Finally, we envision a layered architecture, from the aforementioned hardware layer to an envisioned application layer, providing also examples of what could be done, in the near future, to increase the capabilities of our living spaces.

This work proposes a reconfigurable system able to perform - through a parallel and pipelined core, called ReCPU - regular expression matching. The system can configure on the programmable device, such as a FPGA, a set of ReCPUs, each one exploiting a single instance of the regular expression matching task on the given input string. These cores work in parallel on the same string analyzing different possible matching of the regular expression. Since the system is able to exploit dynamic partial reconfigurations, it can adapt at run-time the number of cores configured on the device, accordingly with the complexity of the regular expression. The adoption of the proposed solution makes it also possible to parallelize the regular expression matching process with a multiple cores architecture drastically reducing the time required for the completion of the task. Finally, run-time reconfiguration capabilities also allow to reduce the amount of resources required by the proposed approach.

Although the reliability and robustness of the AES protocol have been deeply proved through the years, recent research results and technology advancements are rising serious concerns about its solidity in the (quite near) future. In fact, smarter brute force attacks and new computing systems are expected to drastically decrease the security of the AES protocol in the coming years (e.g., quantum computing will enable the development of search algorithms able to perform a brute force attack of a 2n-bit key in the same time required by a conventional algorithm for a n-bit key). In this context, we are proposing an extension of the AES algorithm in order to support longer encryption keys (thus increasing the security of the algorithm itself). In addition to this, we are proposing a set of parametric implementations of this novel extended protocols. These architectures can be optimized either to minimize the area usage or to maximize their performance. Experimental results show that, while the proposed implementations achieve a throughput higher than most of the state-of-the-art approaches and the highest value of the Performance/Area metric when working with 128-bit encryption keys, they can achieve a 84× throughput speedup when compared to the approaches that can be found in literature working with 512-bit encryption keys.

Although the reliability and robustness of the AES protocol have been deeply proved through the years, recent research results and technology advancements are rising serious concerns about its solidity in the (quite near) future. In this context, we are proposing an extension of the AES algorithm in order to support longer encryption keys (thus increasing the security of the algorithm itself). In addition to this, we are proposing a set of parametric implementations of this novel extended protocols. These architectures can be optimized either to minimize the area usage or to maximize their performance. Experimental results show that, while the proposed implementations achieve a throughput higher than most of the state-of-the-art approaches and the highest value of the Performance/Area metric when working with 128-bit encryption keys, they can achieve a 84× throughput speed-up when compared to the approaches that can be found in literature working with 512-bit encryption keys.

Reconfigurable platforms are a promising technology that offers an interesting trade-off between flexibility and performance, which many recent embedded system applications demand, especially in fields such as multimedia processing. These applications typically involve multiple ad-hoc tasks for hardware acceleration, which are usually represented using formalisms such as Data Flow Diagrams (DFDs), Data Flow Graphs (DFGs), Control and Data Flow Graphs (CDFGs) or Petri Nets. However, none of these models is able to capture at the same time the pipeline behavior between tasks (that therefore can coexist in order to minimize the application execution time), their communication patterns, and their data dependencies. This article proves that the knowledge of all this information can be effectively exploited to reduce the resource requirements and the timing performance of modern reconfigurable systems, where a set of hardware accelerators is used to support the computation. For this purpose, this article proposes a novel task representation model, named Temporal Constrained Data Flow Diagram (TCDFD), which includes all this information. This article also presents a mapping-scheduling algorithm that is able to take advantage of the new TCDFD model. It aims at minimizing the dynamic reconfiguration overhead while meeting the communication requirements among the tasks. Experimental results show that the presented approach achieves up to 75% of resources saving and up to 89% of reconfiguration overhead reduction with respect to other state-of-the-art techniques for reconfigurable platforms.

The automatic generation of hardware implementations for a given algorithm is generally a difficult task, especially when data dependencies span across multiple iterations such as in iterative stencil loops (ISLs). In this paper, we introduce an automatic design flow to extract parallelism from an ISL algorithm and perform a design space exploration to identify its best FPGA hardware implementation, in terms of both area and throughput. Experimental results show that the proposed methodology generates hardware designs whose performance is comparable to the one of manually-optimized solutions, and orders of magnitude higher than the implementations generated by commercial high-level synthesis tools.

Wireless Sensor Networks (WSNs) are particular networks characterized by limited energy and computational resources and, if their transmission range is limited to a person's area, they are known as Body Area Networks (BANs). When two or more BANs are co-located and operate on the same channel, active periods can overlap and transmissions can conflict. This phenomenon, that drastically reduces performances and reliability of BANs, is known as BAN-BAN interference. In order to solve this issue, it is possible to employ techniques such as channel switching. However, channel switching is not suitable if the amount of channels is lower than the amount co-located BANs and, considering that interferences of Zigbee/802.15.4 networks with other technologies like 802.11 or Bluetooth reduce the amount of channels available for communication, an alternative approach is required. This paper introduces a BAN-BAN Interference Reduction System (B2IRS) which reschedules beacon packets in order to avoid active period overlap, reducing the interferences between distinct BANs. This approach is complementary to channel switching since it works with single-channel interferences, that arise when no free channels are available anymore. Experimental results, conducted comparing our methodology with the original IEEE 802.15.4, show that B2IRS is able to effectively reduce BAN-BAN interference, making it possible to almost maintain the same performance and energy consumption of an ideal situation (without interferences).

Wireless sensor networks (WNSs) are gradually evolving from a promising technology to a well-established reality in a large set of different domains. In order to fulfill the requirements of the specific scenario, a WSN must provide the right tradeoff between performance and lifetime, which is heavily determined by the network design. However, although the complexity of WSNs is increasing, the design space exploration is often carried out manually without the support of a general analytical methodology. In this paper, we advocate a model-based approach as an efficient and scalable way to explore the energy-performance tradeoffs during the design. In particular, we show that it is possible to define system-level models to describe wide classes of WSNs, providing a quick and accurate network evaluation. As a proof of concept, we propose a general model that describes the main characteristics of a class of WSNs for human health monitoring, and we apply it to a real case study. The results show that the energy-performance estimation error of the model never exceeds 1.74% compared to real data, while the evaluation time is reduced by up to 6 orders of magnitude with respect to an accurate network simulation.

This paper introduces Tacit Consent (TaCo), a technique that exploits spatial correlation in Wireless Sensor Networks in order to reduce energy consumption while maintaining a very high accuracy on the measured data. In fact, nodes densely deployed in a field of interest are proved to sense highly correlated data, thus this intrinsic redundancy can be exploited to predict the neighbors' measurements by defining custom estimation functions, which aim at replicating the relationship between the data sensed by two nodes. To exploit spatial correlation, TaCo splits the nodes into two groups: representative and member nodes. Representative nodes directly transmit their measurements, while member nodes use overhearing to understand whether additional information is required. If the estimation function correctly predicts the measurements of the member nodes, they tacitly consent the estimation without performing any transmission. Differently from the other state-of-the-art approaches, such as the YEAST algorithm, TaCo can be used on top of existing routing and clustering protocols. Experimental results prove that TaCo is able to drastically reduce the energy consumption of the network when a high precision of the measured data is required.

The determination of the optical flow is a central problem in image processing, as it allows to describe how an image changes over time by means of a numerical vector field. The estimation of the optical flow is however a very complex problem, which has been faced using many different mathematical approaches. A large body of work has been recently published about variational methods, following the technique for total variation minimization proposed by Chambolle. Still, their hardware implementations do not offer good performance in terms of frames that can be processed per time unit, mainly because of the complex dependency scheme among the data. In this work, we propose a highly parallel and accelerated FPGA implementation of the Chambolle algorithm, which splits the original image into a set of overlapping sub-frames and efficiently exploits the reuse of intermediate results. We validate our hardware on large frames (up to 1024 × 768), and the proposed approach significantly improves state-of-the-art implementations, reaching up to 76× speedups, which enables real-time frame rates even at high resolutions.

This paper presents a ripple-carry adder module that can serve as a basic component for Quantum Dot Automata arithmetic circuits. The main methodological design innovation over existing state of the art solutions was the adoption of so called minority gates in addition to the more traditional majority voters. Exploiting this widened basic block set, we obtained a more compact, and thus less expensive circuit. Moreover, the layout was designed in order to comply with the rules for robustness again noise paths [6].

Reconfigurable computing is a promising technology that offers an interesting trade-off between flexibility and performance, which many recent multi-core embedded system applications demand. In order to achieve these objectives, it is necessary to optimize the deployment of the hardware cores on the FPGA platform, trying to reduce the reconfiguration overhead while meeting the desired performance. In this paper, we propose a hybrid mapping and scheduling technique for multi-core applications on reconfigurable devices, which exploits the information about the relationships among the application cores to minimize the overhead due to reconfiguration.

Nowadays, multi-core systems-on-chip (SoCs) are typically required to execute multiple complex applications, which demand a large set of heterogeneous hardware cores with different sizes. In this context, the popularity of dynamically reconfigurable platforms is growing, as they increase the ability of the initial design to adapt to future modifications. This paper presents a design flow to efficiently map multiple multi-core applications on a dynamically reconfigurable SoC. The proposed methodology is tailored for a reconfigurable hardware architecture based on a flexible communication infrastructure, and exploits applications similarities to obtain an effective mapping. We also introduce a run-time mapper that is able to introduce new applications that were not known at design-time, preserving the mapping of the original system. We apply our design flow to a real-world multimedia case study and to a set of synthetic benchmarks, showing that it is actually able to extract similarities among the applications, as it achieves an average improvement of 29% in terms of reconfiguration latency with respect to a communication-oriented approach, while preserving the same communication performance.

We present a reconfigurable architecture that can perform highly parallel regular expression matching. The system can be configured on programmable devices such as FPGAs as a set of instances of a predefined core called REMA. Each core addresses one of the subtasks into which the regular expression matching problem can be partitioned. These cores work in parallel on the same string analyzing different possible matchings. Since the system can exploit dynamic partial reconfigurations, it can adapt the number of cores configured on the device at run-time, according to the complexity of the regular expression, which is proportional to the number of different ways in which the reference string can be mapped on pattern. Making it possible to parallelize the matching process with a multiple core architecture drastically improves temporal efficiency (up to one order of magnitude with respect to software solutions and up to a speedup factor of 25 with respect to hardware solutions). Most important, the run-time reconfigurability feature allows to implement a just in time logic usage strategy, thus reducing the mean amount of resources required.

In the last years, the embedded systems market is considerably grown, even though techniques and methodologies for the design of embedded systems, both from the hardware and the software point of view, have not been able to fully support this growth. Within this context, novel methodologies and design flows are required in order both to improve the quality and to shorten the time-to-market of very complex embedded systems.

The role of Field-Programmable Gate Arrays (FPGAs) in System-on-Chip (SoC) design considerably increased in the last few years. Their established importance is due to the large amount of hardware resources they offer, as well as to their increasing performance, and furthermore to the support for reconfigurability. Even though FPGAs seem to have reached their maturity, there is still a lack of Computer-Aided Design (CAD) tools able to deal with dynamic reconfiguration. Existing algorithms aim at optimizing the performance of a set of applications, basing the computation on classic metrics (such as communication overhead), while reconfiguration-related issues are not taken into consideration. This work proposes a design methodology to map several applications on the FPGA area at run-time. Starting from a basic solution found at design-time for the initial set of applications, the proposed algorithm makes it possible to map a new application (not known at design-time), both minimizing the number of synthesis processes and optimizing the on-chip performance of the new application. Experimental results show that the proposed approach is able to achieve up to a 18% reduction in the number of reconfigurations with respect to an off-line static-mapping approach, while generally preserving the performance of the executed applications on the FPGA.

Dynamic reconfiguration capabilities exploited by modern FPGA devices improve the flexibility and the reliability of embedded systems. The increasing complexity demands for a design-paradigm shift towards a communication-centric approach. Networks-on-Chip are a promising design paradigm for both homogeneous and heterogeneous systems in which communication is represented in a network-like manner, even if they cannot directly be applied to the dynamic reconfiguration scenario. While in literature there are different approaches to design communication infrastructures able to support the reconfiguration of its functionalities, what seems to be neglected is the definition of a complete design flow for a dynamic reconfigurable communication infrastructure able to adapt itself at runtime to the current working scenario. This paper proposes a design flow to automatically create a reconfigurable architecture that consists of a grid of homogeneous tiles that can be filled with either computational (master or slave cores with their network interfaces) or communication (switches) elements.

The increasing amount of programmable logic provided by modern FPGAs makes it possible to execute multiple hardware applications on the same device. This approach is reinforced by dynamic reconfiguration, which allows a single part of the device to be configured with a single hardware module. The proposed solution is a Linux-based operating system to manage on-demand module configuration on an FPGA while providing a set of high-level abstractions to user applications. The proposed approach has been validated in a cryptographic context using the DES and the AES algorithms.

Complex design, targeting system-on-chip based on reconfigurable architectures, still lacks a generalized methodology allowing both the automatic derivation of a complete system solution able to fit into the final device, and mixed hardware-software solutions, exploiting partial reconfiguration capabilities. The shining methodology organizes the input specification of a complex system-on-chip design into three different components: hardware, reconfigurable hardware and software, each handled by dedicated sub-flows. A communication model guarantees reliable and seamless interfacing of the various components. The developed system, stand-alone or OS-based, is architecture-independent. The shining flow reduces the time for system development, easing the design of complex hardware/software reconfigurable applications.

Dynamic reconfiguration capabilities of FPGA devices are commonly exploited in order to perform changes in a system with respect to computational elements. In this paper, we propose a framework able to exploit different levels of simulations in order to perform a requirements-driven design of the communication infrastructure of a reconfigurable system, so that the overall performances can be improved. To accomplish this requirements-driven design it is necessary to perform a design space exploration of applications and scenarios in which a particular system can be used. A new scenario-centric approach is proposed in order to identify metrics and requirements needed to apply a communication infrastructure reconfiguration.

One of the main characteristics of reconfigurable embedded systems is their ability to be dynamically modified to be adapted at run-time to the current environment. This feature, that makes it possible to change the functionality of a system while it is up and running, requires a software application that is able to handle the reconfiguration process. The software for the management of reconfiguration can be developed either as a standalone application, that has to be specifically designed for each given system, or within an operating system, in order to fully exploit both code reuse and code portability. This paper proposes a novel methodology for the design of dynamically reconfigurable systems in which the reconfiguration management is completely assigned to an operating system reconfiguration support. Finally, a prototype implementation is presented, where a standard Linux operating system has been extended with the proposed operating system support in order to handle dynamically reconfigurable hardware resources.

Aim of this paper is to propose a reconfigurable processing element based on a Harvard architecture, called HARPE. HARPE's architecture includes a MicroBlaze soft-processor in order to make HARPEs deployable also on devices not having processors on silicon die. In such a context, this work also introduces a novel approach for the management of processor data memory. The proposed approach allows the individual management of data and the dynamic update of the memory, thus making it possible to define partially dynamical reconfigurable multi processing element systems, that consist of several master (e.g., soft-processors, hard-processors or HARPE cores) and slave components. Finally, the proposed methodology enables the possibility of creating a system in which both HARPEs and their memories (data and code) can be separately configured at run time with a partial configuration bitstream, in order to make the whole system more flexible with respect to changes occurring in the external environment.

Reconfigurable hardware is becoming a prominent component in a large variety of SoC designs. Reconfigurability allows for efficient hardware acceleration and virtually unlimited adaptability. On the other hand, overheads associated with reconfiguration and interfaces with the software component need to be evaluated carefully during the exploration phase. The aim of this paper is to identify the best trade-off considering application-specific features in software, which can lend itself to software-based acceleration and lead to a revision of the view that certain computationally intensive tasks can only be accelerated through hardware. In order to validate the effectiveness of our proposed techniques, we built an extensive development and experimental setup, bringing together the MLTon-based programming environment and physical mapping of the software and hardware onto a real dynamically reconfigurable SoC system.

Dynamically reconfigurable hardware allows for implementing systems that can be adapted at run-time according to the needs of the user. This paper presents an architecture that is composed of multiple FPGAs that are connected to an embedded processor. Thus, the architecture is referred to as a multi-FPGA clustered architecture (MFCA). All FPGAs can be partially and dynamically reconfigured to integrate user-defined IP-cores into the system at run-time. For the resource management and communication management we have implemented a Linux operating system on the embedded processor that can be used to control the reconfiguration of the FPGAs by means of simple function calls. Furthermore, the Linux OS completely hides the physical infrastructure of the MFCA from user applications, offering a consistent interface to utilize partial reconfiguration.

Nowadays, dynamic reconfigurable embedded systems are widely used, since they have the capability to modify their functionalities, adding or removing components and modify interconnections among them. The basic idea behind these systems is to have the system autonomously modify its functionalities according to the application's changes. This paper describes the area of reconfigurable embedded systems presenting both architectural and methodological aspects trying to point out common features and needs. After a brief introduction, an overview of the models of the reconfigurable architectures, and of the design methodologies was presented.

This paper aims at defining an adaptive genetic algorithm tailored for the allocation of dynamically reconfigurable modules. This algorithm can be tuned at run-time with a set of parameters to best characterize different architectural scenarios (i.e., single device or multi-FPGAs characterized by several kinds of communication infrastructures) and to adapt the performance of the algorithm itself to the scenario in which it has to operate. The proposed approach has been validated with a large set of meaningful combinations of parameters (i.e. changing the mutation or the crossover probability), in order to demonstrate the possibility of performing either a fast or an accurate allocation phase.

In the face of dominant communication overheads and reconfiguration cost of programmable hardware often deployed in SoC environments, a new paradigm is necessary to revisit the partitioning and allocation problems. Our aim is to integrate generalized performance models into codesign to explore the gray area between hardware and software effectively. We propose to use the adaptive computation approach. Adaptivity implies that due to input changes the output of the system is updated only re-evaluating those portions of the program affected by the changes. We study the impact of our model onto a SoC architecture consisting of embedded processors and dynamically reconfigurable hardware. We present an image processing application mapped onto this architecture as a case study

This paper aims at introducing a methodology that allows an easy implementation of IP-Cores focusing only on their functionalities rather than their interfaces and their integration in a given architecture. The proposed approach implements all the communication infrastructure needed by a component, described in VHDL, to be finally inserted into a real architecture that can be implemented on FPGAs, reducing the time to market of the final implementation of the system. To validate the entire methodology, we have performed a comparison based on the CoreConnect communication infrastructure, between our results with the classical Xilinx design flow using EDK and ISE.

Reconfigurable devices, such as FPGAs, introduce into the design workflow of embedded systems a new degree of freedom: the designer can have the system autonomously modify the functionality carried out by the IP-core according to the application's changing needs while it runs. The Caronte methodology, based on the modular design approach, is a design workflow that allows the creation and the handling of partial dynamic reconfigurable architectures using Xilinx FPGAs. In order to speed up its execution, it is important to succeed in quickly generate the EDK-based systems that the flow requires for the elaboration of the correct partial reconfiguration bitstreams. To achieve this goal, an IP-core generator framework has been developed, it receives as input the VHDL description of the core functionality of a module, automatically produces as output an IP-core suitable to be inserted into an EDK system. This binding can be performed in a faster way than using EDK to re-create each time the entire architecture, exploiting the EDK system creator tool. IP-core generator can be used each time an IP-core has to be created, and not only in a dynamic reconfigurability environment. Several tests are presented to validate the proposed methodology