This innovative practice WIP paper presents a pilot study of an educational intervention designed to transform the way students view and overcome struggles that are a normal-and essential-part of the learning process. The intervention involves sharing “relatable rebound stories” from previous students, each describing a setback or challenge encountered and the specific agentic strategies used to resolve it. Preliminary results are presented from a pilot study conducted in an entry-level computer engineering course of 168 students that requires time management and project-based learning. This study shows the positive impact of this intervention on quantitative sense of belonging and selfefficacy scales and confidence in skills related to computing, systems prototyping, and problem-solving.

Illumination changes present challenging problems to video surveillance algorithms tasked with identifying and tracking objects. Illumination changes can drastically alter the appearance of a scene, causing truly salient features to be lost amid otherwise stable background. We describe an illumination change compensation method that identifies large, stable, chromatically distinct background features-called BigBackground regions - which are used as calibration anchors for scene correction. The benefits of this method are demonstrated for a computationally low-cost kinematic tracking application as it attempts to track objects during illumination changes. The BigBackground-based method is compared with other compensation techniques, and is found to successfully track 60% to 80% more objects during illumination changes. Video sequences of pedestrian and vehicular traffic are used for evaluation.

Traditional video scene analysis depends on accurate background modeling to identify salient foreground objects. However, in many important surveillance applications, saliency is defined by the appearance of a new non-ephemeral object that is between the foreground and background. This midground realm is defined by a temporal window following the object's appearance; but it also depends on adaptive background modeling to allow detection with scene variations (e.g., occlusion, small illumination changes). The human visual system is ill-suited for midground detection. For example, when surveying a busy airline terminal, it is difficult (but important) to detect an unattended bag which appears in the scene. This paper introduces a midground detection technique which emphasizes computational and storage efficiency. The approach uses a new adaptive, pixel-level modeling technique derived from existing backgrounding methods. Experimental results demonstrate that this technique can accurately and efficiently identify midground objects in real-world scenes, including PETS2006 and AVSS2007 challenge datasets.

Automated video surveillance applications require accurate separation of foreground and background image content. Cost sensitive embedded platforms place realtime performance and efficiency demands on techniques to accomplish this task. In this paper we evaluate pixel-level foreground extraction techniques for a low cost integrated surveillance system. We introduce a new adaptive technique, multimodal mean (MM), which balances accuracy, performance, and efficiency to meet embedded system requirements. Our evaluation compares several pixel-level foreground extraction techniques in terms of their computation and storage requirements, and functional accuracy for three representative video sequences. The proposed MM algorithm delivers comparable accuracy of the best alternative (Mixture of Gaussians) with a 6X improvement in execution time and an 18% reduction in required storage.

For multimedia processing, modern instruction-level parallel (ILP) processors are faced with limited parallelism and inevitable communication issues, as silicon feature size decreases and pipelines become wider. In this paper, we propose and evaluate a dynamic optimization mechanism that exploits regular operand distribution patterns in multimedia applications. The proposed methodology i) improves performance by recognizing and extracting more parallelism than conventional ILP processors; ii) lowers the burden of operand transport by localizing the communication between instructions based on the operand characteristics; and iii) maintains binary compatibility by applying run-time optimization rather than requiring changes to the ISA, recompilation with a vectorizing compiler, or manual retargeting and optimization

This paper presents an efficient two-stage filtering method that provides highly reliable 4:2:0 YCbCr signals, which are widely used in the image- and video-processing community. In the first phase, we use an index mapping, center-weighted median filter (IMCWMF) to detect and remove noise from luminance (Y) components while inheriting the chrominance components (Cb and Cr) for the selected median luminance. In the second phase, we use a downsampling sigma filter (DSF) to detect and remove noise from the chrominance components while performing the downsampling process. Simulation results indicate that the proposed method outperforms other nonlinear filters in terms of both noise attenuation and signal-detail preservation while providing accurate color channel information for the JPEG compression process and overall image quality.

As technology trends yield shorter cycle times and larger, wider datapaths in architectures for multimedia systems, global broadcast networks for operand communication are becoming a major bottleneck in processor performance. New low latency operand transport techniques are needed. This paper proposes and evaluates lower cost mechanisms than traditional bypass networks, exploiting regular operand distribution patterns in multimedia applications. To reduce latency associated with operand movement within a datapath, our mechanism, called dynamic instruction clustering, groups chains of dependent instructions within a basic block at runtime, identifies intermediate value transportation, and schedules it on networked ALUs which are connected by a local dedicated network. By converting global communication into local, the transport latency can be minimized and the critical path of the application code can be executed in consecutive, shortened cycles, resulting in improved performance. We demonstrated that 28% and 30% of total dependence edges residing in the instruction window can be localized on 8 and 16-way machines, respectively. Our results show that the overall performance gains over a wide range of multimedia applications are 16% for 8-way and 35% for 16-way on average.

New compact, low-power implementation technologies for processors and imaging arrays can enable a new generation of portable video products. However, software compatibility with large bodies of existing applications written in C prevents more efficient, higher performance data parallel architectures from being used in these embedded products. If this software could be automatically retargeted explicitly for data parallel execution, product designers could incorporate these architectures into embedded products. The key challenge is exposing the parallelism that is inherent in these applications but that is obscured by artifacts imposed by sequential programming languages. This paper presents a recognition-based approach for automatically extracting a data parallel program model from sequential image processing code and retargeting it to data parallel execution mechanisms. The explicitly parallel model presented, called multidimensional data flow (MDDF), captures a model of how operations on data regions (e.g., rows, columns, and tiled blocks) are composed and interact. To extract an MDDF model, a partial recognition technique is used that focuses on identifying array access patterns in loops, transforming only those program elements that hinder parallelization, while leaving the core algorithmic computations intact. The paper presents results of retargeting a set of production programs to a representative data parallel processor array to demonstrate the capacity to extract parallelism using this technique. The retargeted applications yield a potential execution throughput limited only by the number of processing elements, exceeding thousands of instructions per cycle in massively parallel implementations.

A critical problem in wide-issue superscalar processors is the limit on cycle time imposed by the central register file and operand bypass network. Here, a distributed register file architecture that employs fully distributed functional unit clusters is presented. It utilizes a local register mapping table and a dedicated register transfer network to support distributed register operations. In addition, an eager transfer mechanism is developed to reduce penalties caused by incomplete operand transport interconnection. Distributed register files can be employed to reduce operand access time by a factor of two with associated average IPC penalties of 14% and 21% on 4- and 8-way superscalar architectures across a broad range of symbolic, scientific, and multimedia applications. The IPC penalties are only 3% and 10% for SpecINT2000 applications.

The complexity of hardware/software codesign of embedded real-time signal processing systems can be reduced by rapid system prototyping (RSP). However, existing RSP frameworks do not provide a sound specification and design methodology (SDM) because they require the designer to choose the implementation target before specification and design exploration and they do not work together coherently across development stages. This paper presents a new SDM, called MAGIC, that allows the designer to capture an executable specification model for use in design exploration to find the optimal multiprocessor technology before committing to that technology. MAGIC uses a technique called "virtual benchmarking," for early validation of promising architectures. The MAGIC SDM also exploits emerging open-standards computation and communication middleware to establish model continuity between RSP frameworks. This methodology has been validated through the specification and design of a moderately complex system representative of the signal processing domain: the RASSP Synthetic Aperture Radar benchmark. In this case study, MAGIC achieves three orders of magnitude speedup over existing virtual prototyping approaches and demonstrates the ability to evaluate competitive technologies prior to implementation. Transfer of this methodology to the system-on-a-chip domain using Cadence's Virtual Component Codesign infrastructure is also discussed with promising results.

The codesign of embedded real-time signal processing systems is complex.In certain application domains requiring high computational throughput, this complexity is due to the need to employing parallel processing and perhaps using heterogeneous processors.The use of commercial-off-the-shelf (COTS) multiprocessor (MP) hardware and software can reduce codesign complexity.Further complexity reduction can be obtained with emerging synthesis frameworks, which can generate deployable code by leveraging vendor communication and computation libraries.However, these synthesis frameworks are inadequate in providing a sound specification and design methodology (SDM) because they require the designer to first choose the implementation target before specification and design exploration.We have developed a new SDM known as MAGIC that allows the designer to capture the specification in an executable model that can then be used in design exploration to find the optimal COTS MP technology and architecture before committing to that technology.The MAGIC SDM exploits emerging open-standards based VSIPL computation middleware and MPI communication middleware to provide connectivity between specification and design with synthesis frameworks for implementation.This SDM is also shown to be applicable to the system-on-chip (SOC) domain, especially as embodied in a new framework called Virtual Component Co-design from Cadence Design Systems.

Program understanding relates a computer program to the goals and requirements it is designed to accomplish. Application-domain analysis is a source of information that can aid program understanding by guiding the source-code analysis and providing structure to its results. The authors use the term "dowsing" to describe the process of exploring software and the related documentation from an application-domain point of view. They have designed a tool framework to support dowsing and have populated it with a variety of commercial and research tools.

Software evolution is the most costly and time-consuming software development activity, yet software engineering research is predominantly concerned with initial development. MORALE is a development method specifically designed for evolving software. It features an inquiry-based approach to eliciting change requirements, a reverse engineering technique for extracting architectural information from existing code, an approach to impact assessment that determines the extent to which the existing system's architectural components can be reused in the evolved version, a reflective approach to actually perform the evolution, and a specific technique for dealing with the difficulties that arise when evolving user interfaces. MORALE is described in the context of making a specific change to an existing system: adding user-configurable viewers to Version 2.4 of the Mosaic Web browser. Issues that arise are discussed, and the Esprit de Corps tool-suite is described

The various goals and requirements of a system are realized in software as fragments of code that are typically "interleaved" in that they may be woven together in the same contiguous textual area of code. The fragments of code are often delocalized and overlap rather than being composed in a simple linear sequence. Interleaving severely complicates software comprehension and maintenance. To address this problem, we are developing analysis tools, based on the Software Refinery. This paper describes our experiences in detecting interleaving in a corpus of mathematical software written in Fortran from the Jet Propulsion Laboratory. In particular, it discusses how feasible it is to detect interleaving of various types and the ability of existing tools to assist these types of detection.