Demo Data from VLDB 2026 / reviewers in the wild / expert
Wilhelm Anacker
dblp:95/5079
· DBLP profile ↗
1ranked-venue papers
1as first author
0since 2021 · last 1967
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Memory systems · 100% |
Topics — the 2 heaviest of 2, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems
memory hierarchy |
0.0 | 1 | 1967 | Performance Evaluation of Computing Systems with Memory Hierarchies · IEEE Trans. Electron. Comput. 1967 |
Memory systems › memory hierarchy
memory hierarchy performance |
0.0 | 1 | 1967 | Performance Evaluation of Computing Systems with Memory Hierarchies · IEEE Trans. Electron. Comput. 1967 |
Methods — techniques the papers use, named apart from their topics
queueing model · 0.0address trace analysis · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1967 | Performance Evaluation of Computing Systems with Memory HierarchiesabstractData transfers in computing systems with memory hierarchies usually prolong computing time and, consequently, cause degradation of system performance. A method to determine data processing rates and the relative utilization of memories for various system configurations under a variety of program loads is presented. According to this method, a program-independent ultimate data processing rate is derived from characteristics of the processor and the fastest random access memory of the system, and degradation factors are determined by combining statistics of the data flow of actual programs and hardware parameters of the processor and all memories. The statistics of data flow in the memory hierarchy are obtained by analyzing a number of recorded address traces of executed programs. The method presented permits quick evaluation of system performance for arbitrary time periods and for maximum and minimum concurrence of operation of processors and memories. Wilhelm Anacker, Chu Ping Wang |
IEEE Trans. Electron. Comput. | 1 |