Physical layer key generation has attracted considerable attention in the past decade since it provides an alternative solution for the key establishment in wireless networks using channel reciprocity. In this paper we explore the possibility of physical layer key generation for emerging Low Power Wide Area Networks (LPWAN) such as LoRa (Long Range). However, due to the lower transmission rates of LPWANs compared to Wi-Fi and Zigbee, the channel reciprocity is relatively low, which makes timely key generation challenging. To address this problem, we propose a novel information-theoretic key generation scheme that can operate at all data rate settings, featuring a model-based key generation method. Furthermore, we derive an optimal window size to calculate the parameters of the channel model based on a random waypoint model to balance the channel reciprocity and entropy. Extensive evaluations on a campus testbed show that our method can achieve up to 13.8 bps key generation rate. Compared to state-of-the-art methods, the proposed method improves key generation rate by 3x to 5x. We also analyzed the security of the proposed approach and demonstrated it to be resilient to eavesdropping attacks.

In recent years, we have witnessed the rapid development of the long range (LoRa) technology, together with extensive studies trying to understand its performance in various application settings. In contrast to measurements performed in large outdoor areas, a limited number of attempts have been made to understand the characterization and performance of the LoRa technology in indoor environments. In this article, we present a comprehensive study of the LoRa technology in multifloor buildings. Specifically, we investigate the large-scale fading characteristic, temporal fading characteristic, coverage, and energy consumption of the LoRa technology in four different types of buildings. Moreover, we find that the energy consumption using different parameter settings can vary up to 145 times. These results indicate the importance of parameter selection and enabling the LoRa adaptive data rate feature in energy-limited applications. We hope the results in this article can help both academia and industry understand the performance of the LoRa technology in multifloor buildings to facilitate developing practical indoor applications.

There is an increasing interest in Internet of Things (IoT) enabled smart buildings over the past decades. However, the development of smart buildings is impeded by the high installation/maintenance cost and the difficulty of large-scale evaluation in the wild. In this paper, we report the design, implementation, and deployment of an emergency light-based smart building solution. The key advantage of the system is that it is built on the top of the existing facilities in the building (i.e., emergency light). As a case study, we have implemented and deployed our system in nine production smart buildings of different types including residential, commercial office, and warehouse of multiple level building complexes. Using real data from four typical buildings, we show the proposed system can achieve >97% average packet delivery rate. Evaluation results also demonstrate the stability and robustness of the system to environmental changes. The results of this paper provide practical insights to facilitate the development of smart building systems.

An efficient way for computing the response of an adaptive digital filter is to use sliding-block distributed arithmetic (SBDA). One disadvantage of distributed arithmetic is the amount of memory utilized. By encoding the memory tables in offset binary code (OBC), the size of the memory tables is reduced in half. However, the computational workload remains unchanged. By modifying the computational flow, the computational workload can be reduced by almost half at the expense of slightly more memory. This modified SBDA structure is called SBDA-OBC. It has memory requirements 25%-50% lower than SBDA depending on the size of the sub-filter. In terms of the computational workload, SBDA-OBC is most advantageous for large sub-filters and when the filter is split into few subfilters. In this case, the computational workload is reduced almost in half.

We present an implementation of a reconfigurable16-tapfinite impulse response filter for post-processing applications. This filter exploits the distributed arithmetic technique for signal processing and floating-gate voltage references for setting tunable analog coefficients. The filter is fabricated in0.5μmCMOS process, and its order can be increased at the cost of0.011mm2of die area and0.02mWof power per tap. Measurement results for low-pass and band-pass filters at50kHzsampling frequency are presented.

In this paper, an FIR adaptive filter implementation using a multiplier-free architecture is presented. The implementation is based on distributed arithmetic (DA) which substitutes multiply-and-accumulate operations with a series of look-up-table (LUT) accesses. This can be achieved at the cost of a moderate increase in memory usage. The proposed design performs an LMS-type adaptation on a sample-by-sample basis. This is accomplished by an innovative LUT update using a matched auxiliary LUT. The system is implemented on an FPGA that enables rapid prototyping of digital circuits. Implementation results are provided to demonstrate that a high-speed LMS adaptive filter can be realized employing the proposed architecture.

In this paper, an FIR adaptive filter implementation, using a multiplier-free architecture, is presented. The implementation is based on distributed arithmetic (DA) which substitutes multiply-and-accumulate operations with a series of look-up-table (LUT) accesses. This can be achieved at the cost of a moderate increase in memory usage. The proposed design performs an LMS-type adaptation on a sample-by-sample basis. This is accomplished by an innovative LUT update using a matched auxiliary LUT. The system is implemented on an FPGA that enables rapid prototyping of digital circuits. Implementation results are provided to demonstrate that a high-speed, low logic complexity LMS adaptive filter can be realized employing the proposed architecture.