We present a compact model that provides a quick estimation of the stress and mobility patterns around arbitrary configurations of Through-Silicon Via's (TSVs). No separate TCAD simulations are required for these configurations. It estimates nFET and pFET mobility for industry-standard as well as for (100)/substrate orientations. As the model provides mobility info in less than 0.1 millisecond/transistor/TSV, it is possible to be used in combination with layouting tools and circuit simulators to optimise layouts of circuits for digital and analog applications. The model has been integrated into the 3D PathFinding flow, for steering 3D IO placement during stack definition.

The overall design issues for broadband asynchronous transfer mode (ATM) networks are investigated. Three kinds of network design requirements are considered: user grade-of-service (GOS) requirements, network manager requirements, and system designer requirements. The design balance among user, network manager, and designer performance measures is shown. It is shown that the design parameters for broadband ATM exchange can be tuned within the acceptable sets by the layering concept on performance objectives.>