Nowadays, optimal irrigation is essential to maintain global food security because it increases agricultural productivity in areas with limited water availability and makes it possible to grow crops in dry and semi-arid climates. Smart irrigation systems integrate conventional and intelligent control techniques to overcome water scarcity problems. This study reports advancements in intelligent control methods and smart irrigation systems using a hybrid review methodology that combines bibliometric analysis and narrative literature review. The analysis was carried out using VOSviewer software, based on 3,003 publications from 2010 to 2024 that were obtained from the Scopus database using keywords like irrigation system, Internet of Things, artificial intelligence, and sustainability. In conventional controllers such as PID controllers, we emphasize the systems or models with controlled parameters such as soil moisture, climatic factors (like temperature, humidity, and atmospheric pressure), and Soil factors (like fertilizer, pH, and salinity). In addition to this, the intelligent controllers have a learning mechanism, which makes them adaptive, indispensable, and different from conventional controllers. The paper deals with conventional controllers as well as intelligent controllers developed for irrigation to make the system smart, which reduces the wastage of water, improves production, and environmental sustainability in terms of their impact, advantages, key limitations, and future directions.

With an increasing trend in the variation of the primary parameters affecting circuit performance, the need for statistical static timing analysis (SSTA) has been firmly established in the last few years. While it is generally accepted that a timing analysis tool should handle parameter variations, the benefits of advanced SSTA algorithms are still questioned by the designer community because of their significant impact on complexity of STA flows. In this paper, we present convincing evidence that a path-based SSTA approach implemented as a post-processing step captures the effect of parameter variations on circuit performance fairly accurately. On a microprocessor block implemented in 90nm technology, the error in estimating the standard deviation of the timing margin at the inputs of sequential elements is at most 0.066 FO4 delays, which translates in to only 0.31% of worst case path delay.

The problem of designing complex analog circuits is attacked using a hierarchical top-down, constraint-driven design methodology. In this methodology, constraints are propagated automatically from high-level specifications to physical design through a sequence of gradual transformations. Constraint transformation is a critical step in the methodology, since it determines in large part the degree to which specifications are met. In this paper we describe how constraint transformations can be efficiently carried out using hierarchical parameter modeling and constrained optimization techniques. The process supports complex high-level specification handling and accounts for second-order effects, such as interconnect parasitics and mismatches. The suitability of the approach is demonstrated through an 4 th order active filter test case.

An analytical-model generator for interconnect capacitances is presented. It obtains analytical expressions of self and coupling capacitances of interconnects for commonly encountered configurations, based on a series of numerical simulations and a partial knowledge of the flux components associated with the configurations. The configurations which are currently considered by this model generator are: (a) single line; (b) crossing lines; (c) parallel lines on the same layer; and (d) parallel lines on different layers (both overlapping and nonoverlapping).>

A design methodology for the physical design of analog circuits is proposed. The methodology is based on the automatic generation of constraints on parasitics introduced during the layout phase from constraints on the functional performance of the circuit. In this novel performance-constrained approach, the parasitic constraints drive the layout tools to reduce the need for further layout iterations. Parasitic constraint generation involves (1) generation of a set of bounding constraints on the critical parasitics of a circuit to provide maximum flexibility to the layout tools while meeting the performance constraints; and (2) deriving a set of matching constraints on the parasitics from matched-node-pair and matched-branch-pair information in differential circuits. The constraint generator PARCAR is described and results presented for test circuits.>

A well-defined methodology for mapping the constraints on a set of critical coupling capacitances into constraints in the vertical-constraint (VC) graph of a channel is presented. The approach involves directing undirected edges, adding directed edges, and increasing the weights of edges in the VC graph in order to meet crossover constraints between orthogonal segments and adjacency constraints between parallel segments while attempting to cause minimum increase in the channel height due to the constraints. Use is made of shield nets when necessary. A formal description of the conditions under which the crossover and the adjacency constraints are satisfied is provided and used to construct the appropriate mapping algorithms. The problem of imposing matching constraints on the routing parasitics in a channel with lateral symmetry is addressed. It is observed that perfect matching is not possible for a matched pair of nets with intersecting horizontal spans. A technique to achieve almost perfect mirror symmetry is presented for such pairs of nets.>

An approach for generating constraints on interconnect parasitics to drive the routing of analog circuits is presented. The approach involves (a) generation of a set of bounding constraints on the critical parasitics of a circuit to provide maximum flexibility to the router while meeting the performance constraints, and (b) deriving a set of matching constraints on the parasitics from matched-node-pair and matched-branch-pair information on differential circuits. A prototype constraint generator is described. It is hoped that the constraint-based approach suggested in this paper, if applied to both placement and routing, will reduce the need of time consuming layout-extraction-simulation iterations in the physical design phase of analog circuits. >

A well-defined methodology for mapping the constraints on a set of critical coupling capacitances into constraints in the vertical-constraint (VC) graph of a channel is presented. The approach involves directing undirected edges, adding directed edges and increasing the weights of edges in the VC graph, in order to meet crossover constraints between orthogonal segments and adjacency constraints between parallel segments, while attempting to cause minimum increase in the channel height due to the constraints. A technique to match the parasitics for symmetrical pairs of nets in the channel is also proposed.>

A general methodology for the design of the interconnections of analog circuits to meet high-level constraints on performance is described. In this approach, sensitivities of performance to parasitics are computed, and a set of bounding constraints for parasitics is determined. Sensitivities are then used to generate the weights for a cost function-driven analog area router. After the routing is completed, the actual values of critical parasitics are used to check if the user-defined constraints on circuit performance are met. If the requirements have not been satisfied, the bounding constraints generated on the parasitics are used to increase the weights associated with the parasitics which violated the constraints, and the circuit is rerouted. Results validating the effectiveness of this approach for layout-design automation of analog circuits are reported.>