With ever-shrinking device geometries, process variations play an increased role in determining the delay of a digital circuit. Under such variations, a gate may lie on the critical path of a manufactured die with a certain probability, called the criticality probability. In this paper, we present a new technique to compute the statistical criticality information in a digital circuit under process variations by linearly traversing the edges in its timing graph and dividing it into ldquozones.rdquo We investigate the sources of error in using tightness probabilities for criticality computation with Clark's statistical maximum formulation. The errors are dealt with using a new clustering-based pruning algorithm which greatly reduces the size of circuit-level cutsets improving both accuracy and runtime over the current state of the art. On large benchmark circuits, our clustering algorithm gives about a 250times speedup compared with a pairwise pruning strategy with similar accuracy in results. Coupled with a localized sampling technique, errors are reduced to around 5% of Monte Carlo simulations with large speedups in runtime.

This paper presents a new approach to active sub-threshold leakage reduction using task migration. The main idea is to replicate a hot module in a design so as to actively migrate its computation at regular intervals, reducing the on-chip temperature and thereby the sub-threshold leakage. We observe that choosing which blocks to migrate and their placement in a floorplan is a chicken-and-egg problem. To solve this, we propose a two step floorplanning methodology, wherein, given a base floorplan, we first choose the modules to replicate and then effectively utilize the deadspaces in it by exploiting the lateral conduction of heat in the floorplan to place a modulepsilas replica. With an optimized floorplan, using task migration we obtain an average savings of 29% in the active sub-threshold leakage at the expense of about 6% additional area.

We present a new linear time technique to compute criticality information in a timing graph by dividing it into “zones”. Errors in using tightness probabilities for criticality computation are dealt with using a new clustering based pruning algorithm which greatly reduces the size of circuitlevel cutsets. Our clustering algorithm gives a 150X speedup compared to a pairwise pruning strategy in addition to ordering edges in a cutset to reduce errors due to Clark’s MAX formulation. The clustering based pruning strategy coupled with a localized sampling technique reduces errors to within 5% of Monte Carlo simulations with large speedups in runtime.

We present timing-driven partitioning and simulated-annealing (SA)-based placement algorithms together with a detailed routing tool for three-dimensional (3-D) field-programmable gate array (FPGA) integration. The circuit is first divided into layers with a limited number of interlayer vias, and then placed on individual layers, while minimizing the delay of critical paths. We use our tool as a platform to explore the potential benefits, in terms of delay and wire length (WL), that 3-D technologies can offer for FPGA fabrics. Experimental results show, on average, a total decrease of 25% in WL and 35% in delay can be achieved over traditional two-dimensional chips, when ten layers are used in 3-D integration

We present timing-driven partitioning and simulated annealing based placement algorithms together with a detailed routing tool for 3D FPGA integration. The circuit is first divided into layers with limited number of inter-layer vias, and then placed on individual layers, while minimizing the delay of critical paths. We use our tool as a platform to explore the potential benefits in terms of delay and wire-length that 3D technologies can offer for FPGA fabrics. Experimental results show on average a total decrease of 21% in wire-length and 24% in delay, can be achieved over traditional 2D chips, when five layers are used in 3D integration.

This paper introduces a novel 3-Dimensional (3D) vertically integrated adaptive computing system. This 3D-SoftChip is a combination of state-of-the-art processing and interconnection technology. It comprises the vertical integration of two chips (a Configurable Array Processor and an Intelligent Configurable Switch) through indium bump 3D interconnections. The Configurable Array Processor (CAP) is an array of heterogeneous processing elements (PEs) while the Intelligent Configurable Switch (ICS) comprises a switch block, 32-bit dedicated RISC processor for control, on-chip program/data memory, data frame buffer along with a Direct Memory Access (DMA) controller. This paper introduces the 3D-Softchip architecture for real-time communication and multimedia signal processing as a next gene! ration computing system. The paper further describes the up-to-date HW/SW co-design and verification methodology including high level system modeling and architecture exploration of 3D-SoftChip using SystemC in order to determine the optimum hardware specification in the early design stage.