Low-power artificial intelligence (AI) accelerators are being developed to support the battery-operated edge devices at a minimum expense of classification error. However, the testing of such large AI accelerators with traditional techniques is inefficient in achieving the required certifications for Autonomous Driving Assistant Systems (ISO 26262). ISO 26262 sets very stringent requirements on the testing time and fault coverage during the diagnosability of faults leading to system-level failures during in-field testing. This article proposes a test architecture for low-power AI accelerators by reusing the existing data paths for large AI accelerator arrays. As compared to the full scan-DFT, the proposed test architecture reduces the test time and peak test power, which enhances the reliability of the test responses. The proposed technique reduces 1) the switching power by 87%; 2) testing times by 72% on average for cases up to$32\times 32$; and 3) the peak power by 59%. Further, there is an average reduction in the area by 10% for the accelerator.

The reconfigurable scan network standardized by IEEE std. 1687 offers flexibility in accessing the on-chip instruments, which significantly improves the test cost. In this paper, we present a novel time-multiplexed 1687-network architecture that significantly improves the absolute test application time of systems-on-chip at wafer-level as well as package-levels tests. This architecture leverages: 1) the ever increasing tester channel frequency; 2) the allowed test frequencies at the two test levels; and 3) the flexibility offered by the 1687-network. We also present a test-time calculation method for the proposed network architecture and use it in our experiments. Furthermore, we study the effects of the number of time slots on different parameters.

In[1], the corresponding author was incorrect. The correct corresponding author is Sungju Park.

The scan PUF, which is based-on the power-up states of scan flip-flops, had been proposed to overcome security issues of semiconductor ICs. IC identification, one of those security issues, requires decent uniqueness along with reliability and randomness. This paper presents two efficient PUF elements' selection methods for scan PUF: uniqueunanimous selection method and unique-majority selection method. These methods classify the scan cells according to their trend of power-up states and prioritize them to extract PUF elements. For experiments, enrollment and validation is performed on 15 chips, which are fabricated with 65nm CMOS process. A statistical analysis on experiments verifies the performance of proposed selection methods.

The semiconductor aging is one of the serious threats for the reliability of the system. This paper presents an efficient mechanism for predicting the aging effect. The captured data will be unloaded by shift operation, then verified through the aging monitoring operation. Especially the aging level of automotive semiconductor devices can be estimated by controlling the capture timing. Since the aging monitoring function is efficiently on and off during normal operation, power consumption can be reduced significantly compared with other approaches.