LAGER is an integrated computer-aided design system for algorithm-specific integrated circuit design, targeted at applications such as speech processing, image processing, telecommunications, and robot control. LAGER provides user interfaces at behavioral, structural, and physical levels and allows easy integration of novel CAD tools. LAGER consists of a behavioral mapper and a silicon assembler. The behavioral mapper maps the behavior onto a parameterized structure to produce microcode and parameter values. The silicon assembler then translates the filled-out structural description into a physical layout, and, with the aid of simulation tools, the user can fine tune the data path by iterating this process. The silicon assembler can also be used without the behavioral mapper for high-sample-rate applications. A number of algorithm-specific ICs designed with LAGER have been fabricated and tested, and as examples, a robot arm controller chip and a real-time image segmentation chip are described.>

Studies performed on a recently developed adaptive control algorithm for high-performance robots have shown that for an effective implementation, hardware must efficiently support I/O and complex decision-making operations. General-purpose digital signal processors, with their emphasis on high-speed arithmetic computations, do not adequately serve the needs of adaptive control and similar applications. As an alternative the authors have generated a custom circuit for a cost-effective implementation of the algorithm. The generation of the custom circuit is based on a customizable digital signal processor embedded inside a CAD framework for application-specific ICs. With this approach, customized versions of the processor are automatically generated from high-level descriptions of algorithms.>