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VLDB 2026 Research / reviewers in the wild / expert

Venkata S. Rangavajjhala

dblp:96/2364 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1993
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 61% Hardware reliability and fault tolerance · 30% Integrated circuit design · 9%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
hardware verification and test		 0.011993
Statistical degradation analysis of digital CMOS IC's · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1993
Hardware reliability and fault tolerance
process variation and yield analysis		 0.011993
Statistical degradation analysis of digital CMOS IC's · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1993
Electronic design automation › circuit simulation › probabilistic simulation
statistical circuit simulation		 0.011993
Statistical degradation analysis of digital CMOS IC's · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1993
Integrated circuit design › digital circuit design › CMOS circuit design
digital CMOS circuits		 0.011993
Statistical degradation analysis of digital CMOS IC's · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1993

Methods — techniques the papers use, named apart from their topics

switch-level simulation · 0.0statistical analysis · 0.0interval analysis · 0.0
YearPublicationVenuePosition
1993 Statistical degradation analysis of digital CMOS IC's
abstract
A statistical switch-level simulator, based on interval and statistical analysis techniques, that simulates the effects of fabrication process fluctuations and environmental effects on digital CMOS integrated circuits is presented. The simulator is computationally very cost-effective compared to conventional Monte Carlo simulators, yet produces results with equal accuracy. The simulator enables analysis of the sensitivity of critical function and performance levels to a variety of parameter variations, thus providing a basis for establishing correspondence between process control, yield, and reliability.>
Venkata S. Rangavajjhala, Bharat L. Bhuva, Sherra E. Kerns
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1