This paper proposes a multiresolution AHB on-chip bus tracer named SYS-HMRBT (aHb multiresolution bus tracer) for versatile system-on-chip (SoC) debugging and monitoring. The bus tracer is capable of capturing the bus trace with different resolutions, all with efficient built-in compression mechanisms, to meet a diverse range of needs. In addition, it allows users to switch the trace resolution dynamically so that appropriate resolution levels can be applied to different segments of the trace. On the other hand, SYS-HMRBT supports tracing after/before an event triggering, named post-triggering trace/pre-triggering trace, respectively. SYS-HMRBT runs at 500 MHz and costs 42 K gates in TSMC 0.13-m technology, indicating that it is capable of real time tracing and is very small in modern SoCs. Experiments show that the bus tracer achieves very good compression ratios of 79%-96%, depending on the selected resolution mode. As a case study, it has been integrated into a 3-D graphics SoC to facilitate the debugging and monitoring of the system behaviors. The SoC has been successfully verified both in field-programmable gate array and a test chip.

This paper presents a novel approach to make the on-chip instruction cache of a SoC to function simultaneously as a regular instruction cache and a real time program trace compressor. This goal is accomplished by exploiting the dictionary feature of the instruction cache with a small support circuit attached to the side of the cache. The trace compression works in both the bypass mode and the online mode. Compared with related work, this work has the advantage of utilizing the existing instruction cache, which is indispensable in modern SoCs, and thus saves significant amount of hardware resource. The RTL implementation of a 4KB trace-capable instruction cache, a 4KB data cache and an academic ARM7 processor core has been accomplished. The experiments show that the cache achieves average compression ratio of 90% with a very small hardware overhead of 3652 gates. In addition, the trace support circuit does not impact the global critical path. Therefore, the proposed approach is highly feasible on-chip debugging/monitoring solution for SoCs, even for cost sensitive ones such as consumer electronics.

The in-circuit emulator (ICE) is commonly adopted as a microprocessor debugging technique. In this paper, a parameterized embedded in-circuit emulator and its retargetable debugging software are proposed. The parameterized embedded in-circuit emulator can be integrated into different style processors such as microcontroller, microprocessor, and DSP processor. The GUI interface debugging software can help user to debug easily. As a result of it, the duration of microprocessor debugging design procedure time is reduced.

This paper purpose an embedded AMBA signal tracer for microprocessor-based SoC's. This tracer provides five trace resolution modes that can perform a cycle-accurate or a transaction-based trace collection in an unlimited time. Also this tracer is implemented in a Soft-IP style. It provides four parameters for tracing configuration. The experimental results show that the bus tracer can reach a good compression ratio of 96%.

The bus tracing is used to catch related signals for further investigation and analysis. However, the trace size of cycle-accurate tracing is large and the trace cycle is shallow unless using a proper compression mechanism. In this paper, we propose an embedded multi-resolution AMBA trace analyzer that provides the trade-off between the trace granularity and the trace depth. It consists of two major trace approaches: (1) the signal monitor/tracing which provides the levels of abstraction, and (2) the trace reduction. In the first approach, it allows designers to zoom-in/out to preferred level of abstraction to serve different debugging purposes. In the second approach, the trace analyzer compresses the traced data according to signal characteristics and the cost of on-chip storage is reduced. The trace data will be decompressed on the host for further observation and debugging. The experimental results show that the proposed approach can reach a good compression ratio of 96% and the trace depth is more than two thousand cycles at the higher abstraction level.

Address trace compression represents that the address data, which were generated from instruction fetch stage of microprocessor, can be retrieved for later observation and analysis. In this paper, we present how to design and implement this real-time address trace compressor (RTATC), which can be used to collect the address trace information of FPGA Prototyping system based on embedded microprocessors. Address trace compressor is able to monitor address bus of microprocessor, and to get operation workload under the analysis of profiling software. Address trace compressor is also allowed to perform accurate, successive trace collection in an unlimited length and can be used in different embedded microprocessors. At last, by the help of FPGA, this silicon intelligent property can own the abundant reconfigurable parameters, the removable modules and the reusable ability.

In this paper, we o introduce the Reusable Embedded In-Circuit Emulator (EICE) and Reusable EICE development system. The main function in EICE we design are testing and debugging. The architecture of EICE is reusable and based on IEEE 1149.1 boundary scan architecture. The EICE development system can help EICE to reduce developing time while developing a microcontroller/microprocessor. We implemented EICE by ASIC and FPGA way and the development system had been demonstrated in two microcontroller.