Multiple instance regression (MIR) was introduced by Ray and Page (2001) as an analogue of multiple instance learning (MIL) in which we are given bags of feature-vectors (instances) and for each bag there is a bag-label which matches the label of one (unknown) primary instance from that bag. The goal is to compute a hypothesis regressor consistent with the underlying instance-labels. A natural approach is to find the best primary instance assignment and regressor optimizing the mse loss on the bags though no formal generalization guarantees were known. Our work is the first to prove generalization error bounds for MIR when the bags are drawn i.i.d. at random. Essentially, with high probability any MIR regressor with low error on sampled bags also has low error on the underlying instance-label distribution. We next study the complexity of linear regression on MIR bags, shown to be NP-hard in general by Ray and Page (2001), who however left open the possibility of arbitrarily good approximations. Significantly strengthening previous work, we prove a strong inapproximability bound: even if there exists zero bag-loss MIR linear regressor on a collection of $2$-sized bags with labels in $[-1,1]$, it is NP-hard to find an MIR linear regressor with bag-loss $< C$ for some absolute constant $C > 0$. Our work also proposes a model training method for MIR based on a novel weighted assignment loss, geared towards handling overlapping bags which have not received much attention previously. We conduct empirical evaluations on synthetic and real-world datasets showing that our method outperforms the baseline MIR methods.

Three-Dimensional Integrated Circuit (3D IC) based on Through-Silicon-Via (TSV) has brought a drastic change in IC technology. Since TSVs connect different layers of 3D stacks, their proper functioning is an essential prerequisite for system operation. Therefore, testing of TSV is essential for 3D IC. In this article, we propose a cost-effective Built-In Self-Test (BIST) method to test the TSVs of a 3D IC. The test method aims at identifying single and multiple defective TSVs using low test time with small hardware overhead. Further, we introduce a BIST partitioning scheme to reduce the test time and hardware overhead for many TSVs. We also present EBIST, an extended-BIST, to enhance BIST reliability with the least hardware cost. The time cycle needed for testing is calculated and compared with previously proposed methods. The simulation result shows that the proposed BIST reduces the test time by 87% compared to prior works. Moreover, the approach yields reduced area as compared to existing test architecture.

Covert Hardware Trojan Horses (HTH) introduced by malicious attackers during the fabless manufacturing process of integrated circuits (IC) have the potential to cause malignant functions within the circuit. This article employs a Design-for-Security technique to detect any HTHs present in the circuit by inserting tri-state buffers (TSB) in the ICs that inject the internal nets with weighted logic values during the test phase. This increases the transitions in the logic values of the nets within the IC, thereby stimulating any inserted HTH circuits. The TSBs are efficiently inserted in the IC considering various circuit parameters and testability measures to bolster the transitions in logic values of the nets throughout the IC while minimising the area overhead. Simulation results show a significant increase in transitions in logic values within HTH triggers using this method, thus aiding in their detection through side-channel analysis or direct activation of the payload.

Through silicon via (TSV)-based 3-D integrated circuit (3-D IC) has several advantages like high density, high bandwidth, and low-power consumption. However, many defects in TSV are evolved during the fabrication and bonding process. In practice, faulty TSVs tend to be clustered. Employing spare TSVs (s-TSVs) is an acceptable method for repairing faulty TSVs. This article introduces a tree-based TSV repair framework to utilize hardware resources more efficiently for a higher repair rate. The proposed architecture partitions the s-TSVs for a different level of redundancy sharing. Experimental results show that the proposed design consumes 11.01 μm2area per signal TSV to achieve 99.99% yield for 0.05% failure rate. The proposed architecture also exhibits a higher repair rate of 73.33% for heavily clustered faults. Moreover, for the same number of functional and s-TSVs, the proposed approach reduces the delay overhead efficiently compared to the prior works.

Wireless sensor networks (WSNs) provide a significant contribution to the advancement of the Internet of Things (IoT) as it can transfer massive volume of data to the Internet with the help of low-power and low-cost self-operating sensing devices. This article deals with the congestion problem which is one of the critical issues in IPV6 over low-power and lossy wireless personal area network (6LoWPAN)-based network as it causes significant packet loss that leads to degraded throughput and extra energy consumption. We propose a congestion control mechanism for 6LoWPAN by using the noncooperative game theory. The proposed method named noncooperative gaming for energy-efficient congestion control (NGECC) determines the optimal data transfer rate of all the source nodes (leaf nodes) to avoid congestion at the intermediate nodes. NGECC considers both the channel occupation and the buffer overflow as the main factors of the packet loss in the network. For the simulation of the NGECC method, we use Contiki OS and Cooja simulator, which operates based on the IEEE 802.15.4 standard and implements the 6LoWPAN protocol stack. The performance of NGECC has been evaluated by comparing it with the analytical results, the default routing protocol for low-power and lossy network functioning, and two other existing methods. The simulation results show that the NGECC outperforms the existing methods in terms of sending rate of data packets, packet delivery ratio, throughput, weighted fairness index, energy consumption, and delay.

Digital microfluidic biochip is a revolutionizing platform to execute complex bioassay operations concurrently. Dependability is an important feature of digital microfluidic biochip which is used for many safety-critical applications, such as point-of-care health assessment, air-quality monitoring, and food-safety testing. Therefore to ensure the proper functionality of the biochip a robust offline and online testing is required. Testing can be done before manufacturing or concurrently with other bioassay operations. In this work, we are presenting an efficient parallel testing and diagnosis scheme to reveal the location of all the faulty electrodes. Most of the algorithms present in the literature are mainly focused on single fault identification. But the diagnosis of biochip with multiple faults is not addressed properly. Even some of the algorithms have incorrectly classified the non faulty electrode as a faulty electrode. Thus in this paper, we are mainly focusing on the detection of multiple faults, correctly and efficiently. Moreover, this testing method is capable to check the given biochip with other concurrently running bioassay operations.

Digital microfluidic biochip has been developed as a promising alternative to the traditional approach of benchtop biochemical laboratory tests. Dependability is an important attribute for microfluidic biochips that are used for safety-critical applications, such as point-of-care health assessment, air-quality monitoring, and food-safety testing. Therefore, the robust offline and online test techniques are required after manufacturing and during bioassay operations. In this work, we are presenting an image segmentation based testing methodology to detect the catastrophic faults and to locate the faulty cells. The design-for diagnosability scheme is proposed, and it is shown that faults can be located and tolerated by providing alternative paths in biochips. Moreover this testing method also facilitates the testing of a biochip with other bioassay operations running concurrently.

Three-dimensional Integrated Circuit (3D IC) based on through silicon via (TSV) has brought a drastic change in the IC technology. Since TSVs connect different layers of 3D stacks, their proper functioning is an essential prerequisite for the system operation. So, testing of TSV is essential for 3D IC. In this paper a cost-effective Built-in Self-Test (BIST) mechanism is proposed for the post-bond test of TSVs in 3D ICs. The test method aims at identifying single and multiple defective TSVs using low test time with minimum hardware. The time cycle needed for testing is calculated and is compared with previous proposed methods. The simulation result shows that the proposed BIST circuit is beneficial over prior BIST technology in terms of test time cycle and hardware requirement.

Congestion control is considered to be an important issue in wireless sensor networks as congestion can cause packet loss and degrade the throughput of the network. In this work, we have proposed a congestion control mechanism for a tree-based network by using non-cooperative game theory where each leaf node tries to maximize its data sending rate. The objective of the proposed work is to find a unique Nash equilibrium point to get the optimal data sending rate of each leaf node so that no congestion will occur at the destination parent node as long as the service rate of the destination node does not change. This also helps in maximizing the overall throughput of the network. In the proposed work, we consider both the buffer overflow and the channel congestion as the major causes of packet loss. The proposed congestion control method named Non-cooperative Game Theory based Congestion Control (NGTCC) has been simulated and compared with an existing algorithm for both single and multi-path tree networks. Simulation results show that the proposed method performs better than the existing method in terms of data sending rate and throughput.

Three dimensional (3D) integration based on through-Silicon-Via (TSV) is currently evolving as an area of great interest in modern semiconductor industry. 3D integration provides higher performance, bandwidth and lower power consumption. But due to scaling in technology features these chips are more complex. Hence, testing of these 3D integrated circuits (ICs) is a challenging task. Effective test architecture design and optimization techniques are essential to minimize the manufacturing test cost. This paper addresses test architecture optimization and Design-for-Test (DfT) for 3D ICs. We design test wrapper for 3D SOC using minimum number of TSVs. Heuristic algorithms are proposed to minimize test time for 3D SOC. Also, TSVs for test access is limited due to small chip area. To address this issue, algorithms are proposed to minimize overall test time considering all possible partial stacks and complete stack for 3D IC with hard dies under TSV constraint. We next describe strategies to identify faulty TSVs in reduced test time. Finally, we present techniques for recovery of those faulty TSVs in 3D IC.

3D integrated circuit (3D IC) is becoming challenging for increasing power density and design complexity. Due to vertical integration heat dissipation in 3D IC is increased that creates hotspots on chip and hence temperature of the chip is very serious issue. Traditional fan-based cooling technique is insufficient for 3D ICs. Hence inter-die integrated microchannel cooling technique and dummy thermal Through-Silicon-Vias (TSVs) based techniques are used for controlling thermal behaviour of the chip. In this paper, we have proposed two temperature estimation models for 3D IC based on liquid cooled microchannels and thermal TSVs. Experimental results show that thermal simulation using our approach provide same result compared to [1]. For microfluidic cooling, our proposed thermal simulator is much more accurate than proposed model [2] and less than 0.5% error respect to simulation result with COMSOL thermal simulator using the same experimental environment of [2].

Due to higher switching activity within scan chain for scanning in/out of the stimuli/response pair, during testing average and peak power dissipation is much higher than the normal mode operation of a circuit. In our paper we propose a method of reducing dynamic power consumption in scan chain by introducing XOR gate at selected places in the traditional scan chain, there by converting the D flip-flops into T flip-flops temporarily during scan. This approach involves reordering of test vectors but not reordering of the scan cells. Our proposed method is verified with ISCAS89 benchmark circuits, which shows that upto 34% reduction in switching activity within modified scan architecture is possible.

This paper highlights the problem of test-bus power reduction in system-on-chip testing. It has been shown that while the cores are fitted with IEEE 1500 wrapper, transitions occurring within test bus and bypass registers can be comparable to those in the scan-chain. Unlike bus encoding the proposed solution does not use any extra hardware and neither affects the compression ratio, nor test application time. Experimental results on ISCAS89 benchmark circuits show up to 87% saving of transitions occurring in test bus in a Huffman coding based test data compression mechanism. A trade-off mechanism has also been shown between compression and test-bus power consumption.

This paper presents a Genetic algorithm (GA) based solution to co-optimize test scheduling and wrapper design under power constraints for core based System-On-Chips (SOCs). Core testing solutions are generated as a set of wrapper configurations, represented as rectangles with width equal to the number of TAM (Test Access Mechanism) channels and height equal to the corresponding testing time. A locally optimal best-fit heuristic based bin packing algorithm has been used to determine placement of rectangles minimizing the overall test times, whereas, GA has been utilized to generate the sequence of rectangles to be considered for placement. Experimental result on ITC’02 benchmark SOCs shows that the proposed method provides better test time results compared to the recent works reported in the literature.