This article describes the current work to extend the Java processor Java Silicon Machine (JSM) for usage in embedded systems. The JSM is a JavaCard processor supporting all JavaCard bytecodes. The JSM is a fully synthesizable 32 bit processor soft core with a very small footprint. The capability of it's integration in small embedded and automation systems is outlined. Special target platform is the SmartDev system which consists of a Java core interfacing to a wide variety of peripherals. SmartDev is intended to be used in mobile embedded systems for administrational, controlling and measurement purposes.

Sedlak (1987) proposed a modulo multiplication algorithm which is suitable for smart card implementation due to its low latency time. It is based on ZDN (Zwei-Drittel-N) arithmetic using an interleaved serial multiplication and reduction to calculate the product P=AB mod M. It can be shown that the maximum average reduction rate is theoretically limited to 3 bit/operation. In this paper we propose a modified left-to-right signed digit re-coding algorithm to receive an average shift of 4.5 bit/operation. Based on the presented ideas we also propose a modified reduction algorithm giving an average reduction rate of 4.5 bit/operation too. The speed up of our algorithms compared with the original algorithm is therefore 50%.

An efficient implementation of modular exponentiation, i.e., the main building block of many public key cryptographic devices, is achieved by algorithmic optimization of the Montgomery modular multiplication algorithm based on multiple precision such that pre-computation of N'/sub 0/=-N/sub 0//sup -1/ mod W can be avoided. This can be attained by modifications of the multiplier used.

No abstract available.

In 1996, about 600 million IC cards were manufactured worldwide. Due to very small die sizes (max. 25 mm/sup 2/) smartcards encounter more severe restrictions than conventional coprocessors. We study coprocessor architectures for very fast but area efficient modular exponentiation (FME) based on Montgomery multiplication. For assessment purposes we developed an evaluation board containing a 8051 microprocessor, a XILINX FPGA and RAM with variable bus width (8b to 32b). We evaluated these architectures in terms of the main design parameters to ease design decisions for smartcards in arbitrary technologies.