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Sujoy Saraswati

dblp:96/7751 · DBLP profile ↗
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2ranked-venue papers
1as first author
0since 2021 · last 2016
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Software engineering, system software, and programming languages
1 paper
Concurrent programming · 50% Compilers and program optimization · 50%

Topics — the 1 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Concurrent programming › transactional memory
software transactional memory
0.112010
Compiler aided selective lock assignment for improving the performance of software transactional memory · PPoPP 2010

Methods — techniques the papers use, named apart from their topics

points-to analysis · 0.1
YearPublicationVenuePosition
2016 Steal-A-GC: Framework to Trigger GC during Idle Periods in Distributed Systems
abstract
Distributed applications for data analytics have emerged to be a significant growth domain both in terms of technology as well as business relevance. With the advent of Hadoop MapReduce, several distributed execution frameworks have been developed for data analytics and machine learning applications. Many of these frameworks are written in Java, Scala or Python and run on top of the Java Virtual Machine (JVM), leaving them vulnerable to the performance impact of garbage collection (GC) operations. Application pauses induced by the Java GC are notorious in being one of the most important contributors of runtime performance bottleneck for a single process execution. These pauses are present in the distributed scenario as well, though in this case, it is significantly more complex to measure the impact of a GC pause for the overall execution runtime. Typically, in a distributed workload, a GC can result in delayed tasks impacting the overall completion time of the application. We present herein a novel way to preemptively trigger Java GC, stealing idle cycles, so as to prevent future tasks from being impacted by a GC pause during peak execution periods, resulting in improved overall application throughput.
Sujoy Saraswati, Soumitra Chatterjee, Ranganath Ramachandra
HiPC1
2010 Compiler aided selective lock assignment for improving the performance of software transactional memory
abstract
Atomic sections have been recently introduced as a language construct to improve the programmability of concurrent software. They simplify programming by not requiring the explicit specification of locks for shared data. Typically atomic sections are supported in software either through the use of optimistic concurrency by using transactional memory or through the use of pessimistic concurrency using compiler-assigned locks. As a software transactional memory (STM) system does not take advantage of the specific memory access patterns of an application it often suffers from false conflicts and high validation overheads. On the other hand, the compiler usually ends up assigning coarse grain locks as it relies on whole program points-to analysis which is conservative by nature. This adversely affects performance by limiting concurrency. In order to mitigate the disadvantages associated with STM's lock assignment scheme, we propose a hybrid approach which combines STM's lock assignment with a compiler aided selective lock assignment scheme (referred to as SCLA-STM). SCLA-STM overcomes the inefficiencies associated with a purely compile-time lock assignment approach by (i) using the underlying STM for shared variables where only a conservative analysis is possible by the compiler (e.g., in the presence of may-alias points to information) and (ii) being selective about the shared data chosen for the compiler-aided lock assignment. We describe our prototype SCLA-STM scheme implemented in the hp-ux IA-64 C/C++ compiler, using TL2 as our STM implementation. We show that SCLA-STM improves application performance for certain STAMP benchmarks from 1.68% to 37.13%.
Sandya Mannarswamy, Dhruva R. Chakrabarti, Kaushik Rajan, Sujoy Saraswati
PPoPP4