Congestive heart failure (CHF) is an acute syndrome that results from ventricular dysfunction and progresses in four stages. Its timely detection can reverse heart damage and save lives. This work proposes a low-power, computationally efficient VLSI architecture to detect CHF using a single-lead ECG signal for the first time. This architecture employs a novel wavelet function-based electrocardiogram (ECG) feature extraction method and a random forest (RF) classifier, which can classify regular beats from CHF beats using a subject-oriented approach. Using ECG signals from publicly available datasets, BIDMC-CHF and MIT-BIH NSRDB, the proposed architecture achieves 90.5% accuracy, having a power consumption of$0.1~\mu W$when implemented using TSMC 40-nm bulk CMOS technology as an ASIC. The low power consumption of the proposed architecture enables it to be utilized efficiently for real-time ECG analysis in wearable devices.

Modulo polynomial multiplication is an essential mathematical operation in the area of finite field arithmetic. Polynomial functions can be represented as tensors, which can be utilized as basic building blocks for various lattice-based post-quantum cryptography schemes. This paper presents a tensor-based novel modulo multiplication method for multivariate polynomials over$GF(2^{m})$and is realized on the hardware platform (FPGA). The proposed method consumes$6.5\times$less power and achieves more than$6\times$speedup compared to other contemporary single variable polynomial multiplication implementations. Our method is embarrassingly parallel and easily scalable for multivariate polynomials. Polynomial functions of nine variables, where each variable is of degree 128, are tested with the proposed multiplier, and its corresponding area, power, and power-delay-area product (PDAP) are presented. The computational complexity of single variable and multivariate polynomial multiplications are$O(n)$and$O(np)$, respectively, where$n$is the maximum degree of a polynomial having$p$variables. Due to its high speed, low latency, and scalability, the proposed modulo multiplier can be used in a wide range of applications.

Lattice-based homomorphic encryption schemes provide strong resistance against quantum and classical computer-based adversary security attacks. In this article, we present a software-hardware co-design of two partially homomorphic encryption (PHE) schemes employing an ARM-System on Chip (ARM-SoC) and an field programmable gate array (FPGA). This provides necessary acceleration to PHE methods in the ecosystem mentioned above. The first PHE scheme is designed for generic homomorphic encryption, while the second scheme is aimed at resource optimized lightweight IoT-driven applications. For seamless assimilation, a robust and reliable low latency data transfer protocol is developed between the FPGA-based accelerator IP and ARM-SoC host system. The proposed PHE schemes are realized using Verilog hardware description language on multiple FPGA platforms. The proposed lightweight scheme is$52.71\times$more resource-efficient than the pipelined BGV RLWE-based method. It exhibits$1.43\times$and$1.29\times$better throughput than non-pipelined and pipelined realizations of the BGV RLWE-based scheme. The proposed hardware accelerators realized on FPGA platforms having lesser clock speed and consuming lower resources showcase significant speedup compared to their software implementations making our proposed method an efficient alternative to enhance security in edge-enabled IoT devices.

Abstract The security of most early fully homomorphic encryption schemes was based on the hardness of the Learning with Errors (LWE) problem. These schemes were inefficient in terms of per gate computations and public‐key size. More efficient schemes were later developed based on the hardness of the Ring‐LWE (RLWE) problem. While the hardness of the LWE problem is based on the hardness of the approximate shortest vector problem (GapSVP γ ) over regular lattices, the hardness of the RLWE problem is based on the hardness of the approximate shortest vector problem over ideal lattices. As of now, it has not been proved that the (GapSVP γ ) problem over ideal lattices is as difficult as the corresponding problem over regular lattices. In this work, the authors propose a multi‐bit levelled fully homomorphic encryption scheme using multivariate polynomial evaluations whose security depends on the hardness of the LWE problem. In terms of per gate computation cost, this scheme is more efficient than existing LWE‐based schemes. Further, for an appropriate choice of parameters, the per computation cost for homomorphic multiplication can be made asymptotically comparable to RLWE‐based schemes in a parallel computing environment. For homomorphic multiplication, the scheme uses a polynomial‐based technique that does not require relinearization (and key switching).

Given a primitive polynomial$p(x)$, of degree$n$, we deal with the problem of finding the number of possible linear feedback shift register realizations, with m-input m-output delay elements, such that the corresponding characteristic polynomial is$p(x)$. We show the equivalence between these realizations and a set of specially structured matrices. Furthermore, the number of realizations is computed for some special cases.