The landscape of video codecs used by broadcasters for their streaming solutions is constantly evolving. This evolution is resulting in increasingly complex codecs forcing broadcasters to consider solutions based on software codecs, as opposed to those based on hardware codecs, owing to the increased flexibility. Additionally, open-source software encoders for the popular AVC (x264), and emerging HEVC (x265) standards are now sufficiently robust for broadcasters to seriously consider using them for deployment. However, both these encoders, in their stock implementation, use a single set of encoder settings for a given stream without adapting the encoder dynamically to the incoming content. Without this ability, the encoder would have to be configured with conservative settings to sustain the target frame rate, resulting in inefficient encodes that either consume more bits than intended for the given quality, or achieve lower quality than possible for the given bitrate.

During various stages of hardware design, different types of control signals get introduced; clock, reset are specified and connected at the RTL stage whereas signals like scan enable, isolation enable, power switch enable get added to implemented devices later in the flow.

For multimedia SOCs supporting real time, high throughput and data intensive applications, performance validation of memory subsystems is needed to uncover the bottlenecks in the RTL implementation. Traditional validation techniques are either too slow, non-exhaustive (like performance simulations or running pseudo applications on FPGA platforms), or are not accurate enough to guarantee conformance (like abstract interpretation and analysis). In this paper we present an approach for performance validation which uses (a) semi-formal techniques rather than pure simulation for providing a wider coverage, (b) actual RTL implementations wherever available for more accurate analysis, and (c) sequential equivalence checking for validating the abstract models for IP's whose RTL is either not present or from which datapath has been abstracted out. We illustrate this approach using two case studies from video signal processing platforms. In the first study, performance Issues found in silicon were detected using the proposed approach, and in the second study a number of performance bottlenecks were detected much before the RTL was frozen.

Robust verification of protocol conversion and arbitration schemes of SoC bridges forms a significant component of the overall SoC verification. Formal verification provides a way to achieve this, but a naive approach often leads to explosion of the state space, and is impractical for most of today's protocols and bridges. This problem is further complicated in the presence of serial protocols, where control and data are mixed together and transactions continue for very great depths. White-box verification is not a feasible solution, since these bridges are often imported or generated from other sources, and internal information is not readily available. In this paper, we propose a black-box and hybrid approach to this problem, by judiciously mixing simulation and formal verification. We illustrate our approach by applying it to two dual stage bridges that perform serial to parallel protocol conversion and vice versa.