Tiled manycore architectures have become dominant for the integration of tens or even a hundred processor cores on a chip. While commercial products are increasingly available, research on the hardware of such platforms and especially prototyping often rely on building such a platform from scratch or is bound to abstract simulation. In this paper we present the Open Tiled Manycore System-on-Chip (Op-TiMSoC) which is a library-based tool flow that helps generating a tiled manycore platform based on a library of open standard components. OpTiMSoC allows for research and prototyping of both shared memory and distributed memory platforms. It includes LISNoC which is a flexible NoC implementation. An OpTiMSoC system can easily be generated based on the publicly available repository and prototyped on an FPGA. As exemplary targets we evaluated the usage of different FPGA boards and an emulation platform.

Today, Network on Chip concepts principally assume inherent lossless operation. Considering that future nanometer CMOS technologies will witness increased sensitivity to all forms of manufacturing and environmental variations (e.g., IR drop, soft errors due to radiation, transient temperature induced timing problems, device aging), efforts to cope with data corruption or packet loss will be unavoidable. Possible counter measures against packet loss are the extension of flits with ECC or the introduction of error detection with retransmission. We propose to make use of the perceived deficiency of packet loss as a feature. By selectively discarding stuck packets in the NoC, a proven practice in computer networks, all types of deadlocks can be resolved. This is especially advantageous for solving the problem of message-dependent deadlocks, which otherwise leads to high costs either in terms of throughput or chip area. Strict ordering, the most popular approach to this problem, results in a significant buffer overhead and a more complex router architecture. In addition, we will show that eliminating local network congestions by selectively discarding individual packets also can improve the effective throughput of the network. The end-to-end retransmission mechanism required for the reliable communication, then also provides lossless communication for the cores.

With the transition from buses to on-chip networks in SoCs the problem of deadlocks in on-chip interconnects arises. Deadlocks can be caused by routing cycles in the network, or by message dependencies, even if the network itself is actually free of routing cycles. Two basic approaches to counter message dependent deadlocks exist: deadlock avoidance, which is most popular in NoCs, and deadlock recovery, which has until now only been used in parallel computer networks. Deadlock recovery promises low buffer space requirements and does not impose restrictions on connections between individual communication partners. For this study, we have adapted a deadlock recovery scheme for the use in NoCs and compared it to strict ordering as a representative of deadlock avoidance in terms of throughput and buffer space. The results show significant buffer space savings for deadlock recovery, however, at the cost of reduced data throughput.

The concept of on-chip networks (NoCs) has been developed to cope with the increasing communication requirements in systems-on-chip (SoCs) consisting of an ever-growing number of cores. Proposals of NoC architectures are often made assuming evenly distributed traffic, where all tiles receive and produce the same amount of traffic. However, in real systems specific, communication centric tiles, for example off-chip memory controllers or other data IO interfaces, consume and generate a significant part of the overall traffic. In this paper we propose hierarchical NoC topologies to improve access to this type of shared resources. The hierarchical networks may be built from different types of sub-networks, e.g. meshes, rings, crossbars and buses. We investigate different hierarchical network architectures and compare them to the popular 2D mesh topology in terms of hop count, latency and network throughput. Our results show that the proposed approach allows to significantly reduce network latencies to these communication centric tiles.

During the design process of modern SoCs (systems on chip), design tools and methods are required for the exploration of promising solutions. Evaluation criteria in this process are performance and often also power consumption. The design space is expanded by a trend towards time variant SoCs, which adapt their behaviour at run time to improve reliability or power consumption. This paper presents an extension to the TAPES system simulator in order to enable not only the exploration of architectures but also the investigation of power minimization strategies. The usefulness of the simulator is demonstrated in an architecture exploration of a network processor.