Network-on-chip (NoC) has become one of the most common interconnection architectures to integrate multicore system. However, the performance, hardware costs, and power consumption of NoC are sensitive to many parameters, such as topology, the number and depth of virtual channels (VCs), routing algorithms, and flow control mechanisms. In order to find the best NoC solution for different applications, a fast and flexible NoC simulator is necessary. In this article, we present an ultrafast field programmable gate array (FPGA)-based NoC simulator called SRNoC, which is able to be configured via host on PC. In SRNoC, we proposed switch–router architecture and virtual boundary technology. Switch–router is an architecture which makes SRNoC support irregular or custom NoC topology by configuring the NoC topology in hardware. Virtual boundary is a novel configurable virtualization mechanism which can store boundary traffic and use the stored boundary traffic to simulate large NoC in virtualized mode. By employing the switch–router architecture and virtual boundary, SRNoC demonstrates$45\times -3077\times $speed-up against Booksim and maintains the same level of simulation accuracy. This simulator has three main advantages: 1) configured switch–router can support irregular and custom topologies in a nonvirtualized mode; 2) virtual boundary can improve the simulation speed in virtualized mode, effectively; and 3) embedded models can provide evaluation of packet latency, power consumption, and temperature distribution. Due to the switch–router architecture and virtual boundary, SRNoC can simulate a 30-node ($5\times 6$) NoC in nonvirtualized mode and 3072-node ($64\times 48$) in virtualized mode on a Xilinx Virtex-7 FPGA.