We present new methods for the automated learning of heuristics in knowledge lean applications and for finding heuristics that can be generalized to unlearned domains. These applications lack domain knowledge for credit assignment; hence, operators for composing new heuristics are generally model free, domain independent, and syntactic in nature. The operators we have used are genetics based; examples of which include mutation and cross over. Learning is based on a generate and test paradigm that maintains a pool of competing heuristics, tests them to a limited extent, creates new ones from those that perform well in the past, and prunes poor ones from the pool. We have studied three important issues in learning better heuristics: anomalies in performance evaluation; rational scheduling of limited computational resources in testing candidate heuristics in single objective as well as multiobjective learning; and finding heuristics that can be generalized to unlearned domains. We show experimental results in learning better heuristics for: process placement for distributed memory multicomputers, node decomposition in a branch and bound search, generation of test patterns in VLSI circuit testing, and VLSI cell placement and routing.>

A novel search algorithm called band search that generalizes guided depth-first and best-first searches is proposed. The performance of band search is studied, and it is evaluated using six benchmarks. The band-search algorithm and its properties are presented, the conditions when band search behaves like best first search are identified, and possible anomalous behavior when the bandwidth of the search is increased is discussed. The classes of search problems for which band search is applicable are given, and the performance of band search on these problems is evaluated.>

A fault-tolerant model of feed-forward neural computing with mixed-mode redundancy is proposed and analyzed. A mixed-mode redundancy is a combination of spatial redundancy and temporal redundancy. The redundancy is based on the homogeneity of both structures and operations of neurons in neural networks. This fault-tolerant model can be applied to both hardware architecture and parallel software simulation. By storing multiple sets of weights in a neuron and recomputing the outputs of this neuron at other different neurons, faults in the neuron can be detected and the output errors can be corrected. The degree of the fault tolerance of this model is analyzed. Further, the sufficient conditions for detecting errors and recovering outputs are also presented. The model can highly increase the reliability of neural computing so that a fairly large number of faulty neurons can be detected and that the outputs of these faulty neurons can be recovered.>

A search algorithm called real-time search (RTS) for solving combinatorial optimization problems under real-time constraints is presented. The algorithm aims at finding the best possible solution within a given deadline. Since this objective is generally not achievable without first solving the problem, the authors use an alternative heuristic objective that looks for the solution with the best ascertained approximation degree. The algorithm schedules a sequence of guided depth-first searches, each searching for a more accurate solution (based on the approximation degree set), or solutions deeper in the search tree (based on the threshold set), or a combination of both. Five versions of the RTS algorithm for setting approximation degrees and/or thresholds are formulated, evaluated, and analyzed. The authors describe the experimental results obtained for the five versions of RTS.>

A fault-tolerant neural network with hybrid redundancy is proposed and analyzed. A hybrid redundancy is a combination of spatial redundancy, temporal redundancy, and coding. It is based on the homogeneity of both structures and operations of neurons. By storing multiple sets of weights in a processor and by recomputing the outputs of neurons with multiple processors, faults in the processors can be detected and corrected. This architecture can highly increase the reliability of a neural network so that a fairly large number of faulty neurons can be detected and that the outputs of these faulty neurons can be recovered. The redundancy of this architecture is fairly low if only certain critical neurons, such as output neurons, are implemented with this technique