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James H. Pugsley

dblp:97/5246 · DBLP profile ↗
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2ranked-venue papers
1as first author
0since 2021 · last 1981
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 33% Electronic design automation · 33% Processor architecture and microarchitecture · 33%
Theoretical computer science
1 paper
Automata and formal languages · 91% Coding theory · 9%

Topics — the 5 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture › microprogramming
control memory minimization
0.011981
Control Memory Wort Width Optimization Using Multiple-Valued Circuits · IEEE Trans. Computers 1981
Integrated circuit design
digital circuit design
0.011981
Control Memory Wort Width Optimization Using Multiple-Valued Circuits · IEEE Trans. Computers 1981
Electronic design automation
logic synthesis
0.011981
Control Memory Wort Width Optimization Using Multiple-Valued Circuits · IEEE Trans. Computers 1981
Automata and formal languages › finite automata › sequential machines
linear sequential machines
0.011965
Sequential Functions and Linear Sequential Machines · IEEE Trans. Electron. Comput. 1965
Automata and formal languages › finite automata
sequential machines
0.011965
Sequential Functions and Linear Sequential Machines · IEEE Trans. Electron. Comput. 1965

Methods — techniques the papers use, named apart from their topics

multiple-valued logic · 0.0integrated injection logic · 0.0modulo-2 adders · 0.0delay polynomial algebra · 0.0
YearPublicationVenuePosition
1981 Control Memory Wort Width Optimization Using Multiple-Valued Circuits
abstract
The optimization of read-only memory (ROM) digit dimension for microprogrammed digital computers is considered. The design of integrated injection logic (I2L) multiple valued ROMs is reviewed and designs for corresponding digit-line decoders are presented. Results are presented for determining microoperation groupings that achieve the lower bound digit dimension for multivalued encodings, thus extending to arbitrary radix the theory for the binary case. To illustrate the applicability of these results, the microprogram specifications for previously published optimization examples, as well as that for the Digital Equipment Corporation EDP-9, are shown to have optimal encodings using either three- or four-valued ROMs and either ternary- or quaternary-to-binary decoders, resulting in dramatic savings in device count for the control memory portion of the corresponding machine.
Charles B. Silio Jr., James H. Pugsley, Albert B. Jeng
IEEE Trans. Computers2
1965 Sequential Functions and Linear Sequential Machines
abstract
The``state'' of a sequential machine is interpreted as the sequence-to-sequence input-output mapping performed by the machine. Such mappings have been called sequential functions. This concept of state is applied to the theory of binary linear sequential machines. The modulo-2 adders are assumed to have an inherent delay td≥0, and the effects of initial conditions are considered. The pertinent results from the algebra of delay polynomials are summarized, and the state structure of linear sequential functions is outlined. It is shown that every retrospective linear sequential function can be realized using only unit-delay modulo-2 adders, and bounds are derived on the minimum realizable delay between input and output.
James H. Pugsley
IEEE Trans. Electron. Comput.1