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Tien-Chang Hsu

dblp:97/5494 · DBLP profile ↗
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4ranked-venue papers
0as first author
0since 2021 · last 2008
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › physical design › placement
analytical placement
0.112008
NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs With Preplaced Blocks and Density Constraints · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008
Electronic design automation › physical design › placement
mixed-size placement
0.112008
NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs With Preplaced Blocks and Density Constraints · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008
Electronic design automation
physical design
0.112008
NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs With Preplaced Blocks and Density Constraints · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008
Electronic design automation › physical design
placement
0.112008
NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs With Preplaced Blocks and Density Constraints · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008
Electronic design automation › physical design › layout density control
density constraints
0.012008
NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs With Preplaced Blocks and Density Constraints · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2008

Methods — techniques the papers use, named apart from their topics

multilevel framework · 0.1log-sum-exp wirelength model · 0.1conjugate gradient · 0.1
YearPublicationVenuePosition
2008 NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs With Preplaced Blocks and Density Constraints
abstract
In addition to wirelength, modern placers need to consider various constraints such as preplaced blocks and density. We propose a high-quality analytical placement algorithm considering wirelength, preplaced blocks, and density based on the log-sum-exp wirelength model proposed by Naylor and the multilevel framework. To handle preplaced blocks, we use a two-stage smoothing technique, i.e., Gaussian smoothing followed by level smoothing, to facilitate block spreading during global placement (GP). The density is controlled by white-space reallocation using partitioning and cut-line shifting during GP and cell sliding during detailed placement. We further use the conjugate gradient method with dynamic step-size control to speed up the GP and macro shifting to find better macro positions. Experimental results show that our placer obtains very high-quality results.
Tung-Chieh Chen, Zhe-Wei Jiang, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.3
2006 A high-quality mixed-size analytical placer considering preplaced blocks and density constraints
abstract
In addition to wirelength, modern placers need to consider various constraints such as preplaced blocks and density. We propose a high-quality analytical placement algorithm considering wirelength, preplaced blocks, and density based on the log-sum-exp wirelength model proposed by Naylor et al. [20] and the multilevel framework. To handle preplaced blocks, we use a two-stage smoothing technique, Gaussian smoothing followed by level smoothing, to facilitate block spreading during global placement. The density is controlled by white-space re-allocation using partitioning and cut-line shifting during global placement and cell sliding during detailed placement. We further use the conjugate gradient method with dynamic step-size control to speed up the global placement and macro shifting to and better macro positions. Experimental results show that our placer obtains the best published results.
Tung-Chieh Chen, Zhe-Wei Jiang, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang
ICCAD3
2006 NTUplace2: a hybrid placer using partitioning and analytical techniques
abstract
In this paper, we present a hybrid placer, called NTUplace2, which integrates both the partitioning and the analytical (quadratic programming) placement techniques for large-scale mixed-size designs. Unlike most existing placers that minimize wirelength alone, we also control the cell density to optimize routability while minimizing the total wirelength. NTUplace2 consists of three major stages: multilevel global placement, legalization, and detailed placement. To handle mixed-size designs, in particular, we present a linear programming based legalization algorithm to remove overlaps between macros during global placement. Various other techniques are integrated to improve the solution quality at every stage.
Zhe-Wei Jiang, Tung-Chieh Chen, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang
ISPD3
2005 NTUplace: a ratio partitioning based placement algorithm for large-scale mixed-size designs
abstract
In this paper, we present a hierarchical ratio partitioning based placement algorithm for large-scale mixed-size designs. The placement algorithm consists of three steps: global placement, legalization,and detailed placement; it works in a hierarchical manner and integrates net-weighting partitioning, whitespace management, look-ahead bipartitioning, and fast legalization to handle the large-scale mixed-size placement problems. Unlike the traditional partitioning-based technique that is based on balanced partitioning, we apply ratio partitioning in each level. Further, applying the look-ahead bipartitioning technique in each level, we can evaluate the feasibility of the placement for sub-partitions more accurately. Therefore, we can find better ratios for the partitions, leading to easier legalization for the global placement result and finally a better detailed placement solution. Experimental results show the efficiency and effectiveness of our algorithm.
Tung-Chieh Chen, Tien-Chang Hsu, Zhe-Wei Jiang, Yao-Wen Chang
ISPD2