In this paper design details of a RISC neuro-processor are presented. Neural network applications of Hopfield networks, self-organizing feature maps and multilayer feedforward networks (MFNN) are used as benchmarks for performance evaluation of the neuro-processor. Extensive simulations have been carried out to study the cost performance issues of neuro-processor hardware architecture. A quantitative approach is employed in designing cost-effective implementation of the neuro-processor. Special instructions have been provided in the neuro-processor instruction-set to improve the speed of both implementation and execution of neural networks. Instruction-set usage measurements have been used to study the effectiveness of the instruction-set design. Branch behaviour statistics have been studied in order to adopt good branch prediction strategies.

An SBus Multi Tracer (MT) is described, which is based on our previously developed SBus monitoring board (SMB), which can provide timing diagrams for all SBus signals. However, just like any other logic analyzer or a bus analyzer its trace length is limited by the board memory and it is difficult to cope with multi occurrences of trigger patterns in a single application. An effective answer to this problem is to design an SBus Multi Tracer instead of increasing the size of the board memory. An SMB with MT achieves multiple partitions of its tracing memory by tracing a fixed number of events after each trigger. In this way it provides systematic timing information for a series of pattern occurrences in a sequence of system operations. The possible operation of the SMB is enabled by a built-in Field Programmable Gate Array (FPGA) chip, which has access to all SBus signals, and can easily be reconfigured to provide additional triggering patterns.

During the development of computer peripherals which interface to the processor via the system bus it is often necessary to acquire the signals on the bus at the hardware level. It is difficult to attach general-purpose logic analysers and in-circuit emulators to a multiple pin bus connector and hence it is not practical to catch all the bus data required to ensure that such signals are in accordance with the bus specification. Hence a given connector specific bus monitor board is a necessary instrument to attach to the system motherboard in order to monitor all bus activities. A connector specific bus monitor board provides an efficient resource with which to study the internal philosophy of system software, the software implementation process for different communication layers, and to provide debugging for hardware developers. The bus monitor board described here is designed to attach to a SUN SBus and is similar to the Transformable Computer, which appeared recently, in that its architecture is reconfigurable via the use of a Field Programmable Gate Array (FPGA). It can be programmed to customise it to various users' specific needs. It differs from the Transformable Computer in that although it can be programmed to function as a coprocessor its primary function is dedicated SBus Monitoring. It is less costly than a Transformable Computer.

To produce reliable software, its complexity must be controlled by suitably decomposing the software system into smaller subsystems. A software complexity metric is developed that includes both the internal and external complexity of a module. This allows analysis of a software system during its development and provides a guide to system decomposition. The basis of this complexity metric is in the development of an external complexity measure that characterizes module interaction.>