In this paper, we present reconfigurable multiprocessor architecture for volume rendering. The multiprocessor consists of sixteen reconfigurable processors to exploit data parallelism of the volume rendering. Each processor has VLIW core and reconfigurable coarse-grained array specialized for control and data-intensive part of the program, respectively. The coarse-grained array can be configured dynamically, so that it can efficiently process different kernels of the volume rendering. The multiprocessor is implemented using verilog HDL and realized onto a commercial FPGA-based prototyping system. The experimental result shows that the presented multiprocessor has comparable performance to high-end desktop GPUs.

This paper presents design and implementation of a pipelined datapath for real-time face detection using cascades of boosted classifiers. We propose following methods: symmetric image downscaling, classifier sharing, and cascade merging, to achieve the desired processing speed and area efficiency. First, an image pyramid with 16 levels is generated from the input image to simultaneously detect faces with different scales. The downscaled images are then transferred to the first stage of the cascade that is shared between the corresponding image pairs based on the pixel validity of the symmetric image pyramid. The last method exploits the different hit ratios of the cascade stages. We use a tree-structured cascade of classifiers since most of the nonface elements are eliminated during the early stages of the classifier. The use of a synthesis tool confirms that the proposed design reduces resource utilization by one-eighth without accuracy loss, compared to the fully parallelized implementation of the same algorithm. We implemented the proposed hardware architecture on a Xilinx Virtex-5 LX330 FPGA. The indicative throughput is 307 frames/s irrespective of the number of faces in the scene for standard VGA (640 × 480) images with an operating frequency of 125.59 MHz. We may ensure that face detection results are generated at each clock cycle after the initial pipeline delay, using this fully pipelined datapath for tree-structured cascade classifiers.

Optical flow is a motion field estimation method that has a wide range of applications. In this paper, we present a fully pipelined hardware architecture for high-speed optical flow estimation based on a full-search block matching algorithm. A census transform is applied to the corresponding pixels in the current and previous frame. The similarity between two census vectors within the search area is then computed by measuring the hamming distance. Macro blocks are generated based on the measured hamming distance values and the best match is determined by locating the block that has the smallest sum. The synthesis tool reported that the proposed system is capable of processing 400 standard VGA frames per second.

Recent advances made in IT technology has given much impetus to the development of multimedia devices. The digital camera is such a multimedia device. It has made much progress and become very popular, as most people now own a digital camera or cell phone with camera features. People often take photographs in everyday life. Professional photographers often take photographs of travel destinations, banquet halls or parties. In this paper, we propose an autonomous robot photographer capable of taking pictures and thus replacing photographers. This photographer robot can detect direction based on the human voice. It can control composition based on skin color detection to snap the picture.

Stereo vision is a well-known ranging method because it resembles the basic mechanism of the human eye. However, the computational complexity and large amount of data access make real-time processing of stereo vision challenging because of the inherent instruction cycle delay within conventional computers. In order to solve this problem, the past 20 years of research have focused on the use of dedicated hardware architecture for stereo vision. This paper proposes a fully pipelined stereo vision system providing a dense disparity image with additional sub-pixel accuracy in real-time. The entire stereo vision process, such as rectification, stereo matching, and post-processing, is realized using a single field programmable gate array (FPGA) without the necessity of any external devices. The hardware implementation is more than 230 times faster when compared to a software program operating on a conventional computer, and shows stronger performance over previous hardware-related studies.

This paper presents an FPGA-based parallel hardware architecture for real-time face detection. An image pyramid with twenty depth levels is generated using the input image. For these scaled-down images, a local binary pattern transform and feature evaluation are performed in parallel by using the proposed block RAM-based window processing architecture. By sharing the feature look-up tables between two corresponding scaled-down images, we can reduce the use of routing resources by half. For prototyping and evaluation purposes, the hardware architecture was integrated into a Virtex-5 FPGA. The experimental result shows around 300 frames per second speed performance for processing standard VGA (640times480times8) images. In addition, the throughput of the implementation can be adjusted in proportion to the frame rate of the camera, by synchronizing each individual module with the pixel sampling clock.

Skin color is widely used in many applications because of its merit in human-machine interactions. However, detecting skin color requires repetitive operations on all pixels in the image, similar to other vision-based applications. Since the per-pixel processing is difficult to perform efficiently in conventional computers, many real-time image processing applications have problems with performance. In this paper, we propose FPGA implementation of a real-time skin color detection system. Among the various skin color detection methods, we chose a parametric skin distribution modeling method based on a Gaussian mixture, due to its acceptable training amount and skin detection performance. In addition, a mean-based surface flattening method was also proposed and implemented to improve the detection performance. The proposed method flattens the surface of objects in the scene by replacing the pixel value with the mean of its similar neighborhoods to remove the color noise. After this flattening process, the pixel values of the analogous adjacent pixels are located within a narrow range and are easily segmented to a different region. To consider the inherent parallelism of local image processing, all these functions are implemented within the FPGA to meet the demands of real-time performance.

Object tracking is a challenging problem in a number of computer vision applications. A number of approaches have been proposed and implemented to track moving objects in image sequences. The particle filter, which recursively constructs the posterior probability distributions of the state space, is the most popular approach. In the particle filter, many kinds of features are used for tracking a moving object in cluttered environments. The specific feature for tracking is selected according to the type of moving object and condition of the tracking environment. Improved tracking performance is obtained by using multiple features concurrently. This paper proposes the particle filter algorithm, using multiple features, such as IFD (inter-frame difference) and gray level, to track a moving object. The IFD is used to detect an object and the gray level is used to distinguish the target object from other objects. This paper designs the circuit of the proposed algorithm using VHDL (VHSIC hardware description language) in an FPGA (field programmable gate array) for tracking without considerable computational cost, since the particle filter requests many computing powers to track objects in real-time. All functions of the proposed tracking system are implemented in an FPGA. A tracking system with this FPGA is implemented and the corresponding performance is measured

Particle filters have attracted much attention due to their robust tracking performance in cluttered environments. Particle filters maintain multiple hypotheses simultaneously and use a probabilistic motion model to predict the position of the moving object, and this constitutes a bottleneck to the use of particle filtering in real-time systems due to the expensive computations required. In order to track moving objects in real-time without delay and loss of image sequences, a particle filter algorithm specifically designed for a circuit and the circuit of the object tracking algorithm using the particle filter are proposed. This circuit is designed by VHDL (VHSIC hardware description language), and implemented in an FPGA (field programmable gate array). All of the functions of the proposed particle filter used to track moving objects are implemented in the FPGA. The object tracking system employing this circuit is implemented and then its performance is measured

Abstract Over the last decade there has been a tremendous advance in the theory and practice of role‐based access control (RBAC). One of the most significant aspects of RBAC can be viewed from its management of permissions on the basis of roles rather than individual users. Consequently, it reduces administrative costs and potential errors. The management of roles in various RBAC implementations, however, tends to be conducted on an ad hoc basis, closely coupled with a certain context of system environments. This paper discusses the development of a system whose purpose is to help manage a valid set of roles with assigned users and permissions for role‐based authorization infrastructures. We have designed and implemented the system, called RolePartner. This system enables role administrators to build and configure various components of a RBAC model so as to embody organizational access control policies which can be separated from different enforcement mechanisms. Hence the system helps make it possible to lay a foundation for role‐based authorization infrastructures. Three methodological constituents are introduced for our purposes, together with the design and implementation issues. The system has a role‐centric view for easily managing constrained and hierarchical roles as well as assigned users and permissions. An LDAP‐accessible directory service was used for a role database. We show that the system can be seamlessly integrated with an existing privilege‐based authorization infrastructure. Copyright © 2004 John Wiley & Sons, Ltd.

In this paper we present an approach to modeling system-centric information in order to facilitate role engineering (RE). In particular, we first discuss the general character-istics of the information required in RE. Afterwards, we discuss two informational flow types among authorities in-volved in RE process, forward information flow (FIF) and backward information flow (BIF), together with the intro-duction of an information model which is greatly suitable for use in the backward information flow. System-centric information is incorporated in the information model and UML extension mechanisms are exploited for modeling the information. Not only can the information model provide those different authorities with a method for both analy-sis of resources and communication of knowledge in the RE process, but it can also help lay a foundation for successful implementations of RBAC.