Demo Data from VLDB 2026 / reviewers in the wild / expert
Shi-Sen Chang
dblp:97/6443
· DBLP profile ↗
2ranked-venue papers
0as first author
0since 2021 · last 2000
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › hardware verification and test › testability analysis
controllability and observability |
0.0 | 1 | 2000 | TAIR: testability analysis by implication reasoning · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2000 |
Electronic design automation
hardware verification and test |
0.0 | 1 | 2000 | TAIR: testability analysis by implication reasoning · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2000 |
Electronic design automation › hardware verification and test
testability analysis |
0.0 | 1 | 2000 | TAIR: testability analysis by implication reasoning · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2000 |
Electronic design automation › hardware verification and test › fault testing
stuck-at fault testing |
0.0 | 1 | 2000 | TAIR: testability analysis by implication reasoning · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2000 |
Methods — techniques the papers use, named apart from their topics
signal correlation rules · 0.0implication reasoning · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2000 | TAIR: testability analysis by implication reasoningabstractTo predict the difficulty of testing a wire stuck-at fault, testability analysis algorithms provide an estimated testability value by computing controllability and observability. In most common previous work such as COP and SCOAP, signal correlation between controllability and observability is not well handled. As a result, the estimated values can be quite inaccurate, On the other hand, some previous work can take into account signal correlation but may require more CPU time. This paper discusses an efficient method for testability analysis improvement. Our algorithm starts with results obtained from conventional testability analysis such as COP. For each stuck- at fault, we gradually refine these results by recursively applying some simple signal correlation rules. Experimental results show that, with reasonable run-time overhead, significant improvement for testability analysis can be achieved. Shih-Chieh Chang 0001, Wen-Ben Jone, Shi-Sen Chang |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 3 |
| 1998 | A novel combinational testability analysis by considering signal correlationabstractTo predict the difficulty of testing a wire stuck-at fault, testability analysis algorithms provide an estimated testability value by computing controllability and observability. In all previous work, signal correlation between controllability and observability is generally ignored. As a result, the estimated value can be inaccurate. This paper discusses an efficient method to take into account signal correlation for testability analysis. Our experimental results have shown that, with little run time overhead, significant improvement of testability analysis can be achieved. Shih-Chieh Chang 0001, Shi-Sen Chang, Wen-Ben Jone, Chien-Chung Tsai |
ITC | 2 |