This paper proposes an improved PSO (IPSO) algorithm for home energy management system (HEMS), which integrates demand response (DR) in a smart grid. Based on the time of use (TOU), the critical peak pricing (CPP), as well as the DR signals from the utility, the proposed IPSO algorithm minimizes the electricity payment by scheduling the home appliances, while satisfying the constraints set by the users. In order to find better solution, the IPSO adopts new strategies regarding initialization, chaotic inertial weight approach (CIWA), simplex crossover operation, subswarms, repair algorithm, as well as penalty factor in the evolutionary process. To verify the proposed algorithm, simulations are carried out on different kinds of households in a micro-grid, containing some important appliances, EVs, energy storage batteries, photovoltaic (PV) and wind-turbine generations. The simulation results show that the proposed algorithm achieves less electricity payments for the users, while reducing the peak demand of the distribution transformer, with minimal impacts on the users' life. As compared with the existing algorithm, the proposed algorithm is also shown to be able to find better solution for the same number of functions evaluated.

This paper presents a low complexity digit-serial GF(2m) multiplier. The proposed architecture use digit-serial combination Karatsuba multiplier to reduce area complexity of the circuit. This circuit is suitable for elliptic curve cryptography (ECC) technology. We know that the password system operation core is a multiplier. However that password system multiplier is very big, so it is necessary to reduce the area and time complexity. Therefore, this paper design and implement three smaller multipliers and digit-serial in FPGA to reduce time and area complexity. This method uses 3dm/2 ANDs, (6m+n+3dm/2+m/2+d-7) XORs and (3m-3) registers. Take GF(2340) example, the proposed method compares with related works [12] and [14] which can reduce 70.7% and 50.79% on area, respectively and reduce 50.9% and 73.5% on time, respectively.

Power consumption is known to be a crucial issue in current IC designs. To tackle this problem, Multiple Dynamic Supply Voltage (MDSV) designs are proposed as an efficient solution for power savings. However, the increasing variability of clock skew during the switching of power modes leads to an increase in the complication of clock skew reduction in MDSV designs. In this article, we propose a load-balanced clock tree synthesizer with Adjustable Delay Buffer (ADB) insertion for clock skew reduction in MDSV designs. The clock tree synthesizer adopts the Minimum Spanning Tree (MST) metric to estimate the interconnect capacitance and execute the graph-theoretic clustering. The power-mode-guided optimization is also embedded into the clock tree synthesizer for improving additional area overhead in the step of ADB insertion. After constructing the initial buffered clock tree, we insert the ADBs with delay value assignments to reduce clock skew in MDSV designs. The ADBs can be used to produce additional delays, hence the clock latencies and skew become tunable in a clock tree. An efficient algorithm of ADB insertion for the minimization of clock skew, area, and runtime in MDSV designs has been presented. Comparing with the state-of-the-art algorithm of ADB insertion, experimental results show maximum 42.40% area overhead improvement. With the power-mode-guided optimization, the maximum improvement of area overhead can increase to 47.87%.

As the VLSI technology node advances into the nanometer era, reducing the yield loss induced by via failures is one of the critical problems in design for manufacturability (DFM). Double-via insertion (DVI) in the post-routing stage is a highly recommended method by foundries for improving yield and reliability. This work applies the DVI method in the post stage of an X-architecture clock routing to improve via yield. The proposed DVI-X algorithm constructs the bipartite graphs of the partitioned clock routing layout with single vias and redundant-via candidates (RVCs). Then, a set of maximum cliques is obtained from the bipartite graph for solving the DVI problem. Experimental results on benchmarks indicate that DVI-X can achieve higher double-via insertion rate by 2.925% than other works.

As the operation frequency reaches gigahertz in very deep-submicron designs, the effect of on-chip inductance on circuit performance can no longer be neglected. Therefore, it is desired to extract interconnect impedance and inductance accurately. Most previous works on impedance and inductance extraction are based on rectangular discretization which has been shown effective for the classical Manhattan based IC interconnect structures. As technology advances, however, more general IC interconnect structures, such as the X-based interconnect structure, have been in production. Those general interconnect structures allow wires to be routed with non-Manhattan shapes. For the non-Manhattan interconnect structures, rectangular discretization is obviously not sufficient. In this paper, we propose to use the surface integral formulation with triangular discretization to extract impedance and inductance for the general IC interconnect structures. Comparative studies with the well-known FastImp and IE3D show that our approach is flexible and effective.

The paper presents a current-mode CMOS image sensor embedded smooth spatial filter algorithm. The sensor includes a 66/spl times/66 pixel array with an on-chip 6-bit analog-to-digital converter that can identify the output value of pixels in gray level resolution. The last row of pixel cells (1/spl times/66) based on the double sampling is used for reducing fixed pattern noise (FPN). Processing circuits are dedicated for the spatial filter algorithm and support reusability to increase the image processing speed and to reduce the design complexity and chip area. The sensor chip has been designed and implemented in TSMC 0.35/spl mu/m 2P4M CMOS mixed-mode process. Each pixel occupies a area of 15.8/spl mu/m/spl times/10.6/spl mu/m with a fill factor of 37.2%. The power consumption is 35.15mW when the sensor operates at 175 frames/second.

The paper first analyzes the crosstalk interaction for two RLC-based clock routings with considering both coupling capacitance and mutual inductance. Running results based on 0.13/spl mu/m process show our observations: (a) the difference between clock delays in different frequencies is very small because the damped factor is always larger than 1 for a long-wire clock routing; (b) the crosstalk interaction can be ignored when two parallel segments are far away over than 23/spl mu/m because the difference between segment delays in a unit length is always less than 3%; (c) the clock delay and skew of two-clock routing with considering crosstalk interaction increase up to 19.1% and 108.8%, respectively. Then, we propose a coupling aware algorithm to generate two-clock routing with considering crosstalk minimization simultaneously. Experimental results show that the clock delay and skew can be improved up to 4.4% and 20%, respectively, than that of no any crosstalk minimization.

The segmented channel-routing problem arises in the context of row-based field programmable gate arrays (FPGAs). Since the K -segment channel-routing problem is NP-complete for K ≥ 2, an efficient algorithm using the weighted bipartite-matching approach is developed for this problem. Connections that;form a maximum clique are chosen first to be routed to the segmented channel. Then, another maximum clique of the remained connections is routed until all connections have been processed. In addition, a powerful “unroutability check” algorithm is uniquely proposed to tell whether the horizontal switches in an interval of the segmented channel are sufficient for routing or not. Hence, we can precisely discriminate the routable and the unroutable ones from all the test cases. As shown in the experiments, average discrimination ratios of 98.8% and 99.4% are obtained for the 2-segmentation and 3-segmentation models, respectively. Moreover, when applying our routing algorithm to the analyzed nonunroutable cases, a routing failure ratio of 1.5% is reported for the 2-segmentation model, compared to Zhu and Wong's 5.9%; also, a routing failure ratio of 0.8% (less than their 4.7%) is obtained for the 3-segmentation model. In total, the routing failure ratio of our routing algorithm is less than 21% of Zhu and Wong's.

A Pin-Grid-Array (PGA) package router is presented in this paper. Given a chip cavity with a number of I/O pads around its boundary and an equivalent number of pins distributed on the substrate, the objective of the router is to complete the planar interconnection of pad-to-pin nets on one or more layers. This router consists of three phases: layer assignment topological routing, and geometrical routing. Examples tested on a windows-based environment show that our router is efficient and can complete the routing task with less substrate layers. Compared to manual routing, this router features a friendly graphic user interface and can be practically applied to VLSI packaging.

In this paper, a new two-level bipartitioning algorithm TLP, combining a hybrid clustering technique with an iterative improvement based partitioning process, is proposed. The hybrid clustering algorithm consisting of a local bottom-up clustering technique to merge modules and a global top-down ratio-cut technique for decomposition can be used to reduce the partitioning complexity and improve the performance. To generate a high-quality partitioning solution, a module migration based partitioning algorithm MMP is also proposed as the base partitioner for the TLP algorithm. The MMP algorithm implicitly promotes the move of clusters during the module migration processes by paying more attention to the neighbors of moved modules, relaxing the size constraints temporarily during the migration process, and controlling the module migration direction. Experimental results obtained show that the TLP algorithm generates stable and high-quality partitioning results. The TLP algorithm improves the unstable property of module migration based algorithms such as FM and STABLE in terms of the average net cut value. On the other hand, TLP outperforms MELO, GFM/sub t/ and CDIP/sub LA3/ by 23%, 7%, and 10%, respectively and is competitive with hMetis, ML/sub c/ and LSR/MFFS which have generated better results than many recent state-of-the-art partitioning algorithms.

An even-wiring router for the BGA package is presented to interconnect each I/O pad of a chip to a corresponding ball distributed on the substrate area. The major phases for the router consist of layer assignment, topological routing, and physical routing. Using this router, we can generate an even distribution of planar and any-angle wires to improve manufacturing yield. We have also conducted various testing examples to verify the efficiency of this router. Experiments show that the router produces very good results, far better than the manual design, thus it can be practically applied to VLSI packaging.

Given a die with I/O pads wire bonded onto the multilayer substrates of a pin grid array (PGA) package, a three-step net-even-wiring system (NEWS) is proposed to complete the routing of the bond pads to the corresponding grid pins on one or more layers. First, we performed a maximum-cut partitioning on a net interference graph for the layer assignment step. Second, nets on each layer were converted to planar sketches using a novel insertion sort method. Last, the planar sketches were transformed into a net-even-wired layout using a simplified rubber-band router.

A fast and efficient algorithm for technology mapping of electrically programmable gate arrays (EPGAs) is proposed. This Hmap algorithm covers the Boolean network with programmed logic modules bottom-up. The covering operation is based on collapsing the fanins of a node to form a bigger supernode such that fewer clusters are needed to be detected. Then Boolean matching is used to detect whether the collapsed supernode can be mapped into a logic module by looking up an extended GBDD hash table. The use of this table look-up matching can shorten the matching time significantly. As shown in the experiments, the average running time of Hmap is 20 times faster than that of MIS-pga2.

In this paper, we propose a heuristic algorithm for a given topology of a multisource multisink bus to reduce the signal delay time. The algorithm minimizes the delay by inserting buffers into the candidate locations and sizing the buffers. When compared with the traditional method of source driver sizing, experiments show up to 7.2%, 20.7%, and 29.6% improvement in delay for 2.0, 0.5, and 0.3 /spl mu/m technologies, respectively.

No abstract available.

An H-V alternating router based on the concurrent H (horizontal) and V (vertical) tile expansions is presented. The router is modeled by a sequence of alternating H and V corner-stitching space tiles, where the expansion direction is controlled by a heuristic evaluation function using the A* technique and the damping concept. Tile growing is governed by the following three factors: constrained expansion area, limited expansion depth, and oriented expansion direction. All the H-V tile expansion operations can be easily performed on a specially designed net-forest structure. It is shown that this approach generates nearly optimal connection paths with a minimum number of bends and always guarantees a feasible solution if such a path exists. The performance of this router is better than that of H-only tile-expansion routers. This router is also well suited for wiring hierarchical modules with the metal-metal matrix technology and can be extended to multilayer layouts.>

The authors present a novel plane-sweep algorithm based on spatial data structures with region query operations. Such an algorithm is applicable to the problems of VLSI layout design and image processing. It has a computing time of O(N log N) and allows the functional operations of region search of the spatial data structures to be useful in solving some of the specified problems. This algorithm has been successfully implemented in C language; it was based on two kinds of spatial data structures; multiple storage quad tree and quad list quad tree. This plane-sweep algorithm also has been successfully applied to problems of layout compaction, design rule checking, and minimum reliable partition.>