MANBIS is a C++ mathematical software package for tackling the problem of computing the roots of a function when the number of roots is very large (of the order of hundreds or thousands). This problem has attracted increasing attention in recent years because of the broad variety of applications in various fields of science and technology. MANBIS applies the bisection method to obtain an approximate root according to a predetermined accuracy. Thus, the only computable information required is the algebraic signs of the considered function, which is the smallest amount of information (one bit of information) necessary for the purpose needed, and not any additional information. MANBIS is able to compute very efficiently a user-given percentage of roots and draws its strength from the fact that the roots are expected to be many. Furthermore, MANBIS is capable of estimating without any additional function computational cost the total number of roots within the user-given interval. Our approach can also be efficiently applied in cases where the distribution of the roots is not known. This article is accompanied by another article where the user manual, some implementation details, and some examples are included.

Built-In Self-Test (BIST) techniques constitute an effective and practical approach for VLSI circuits testing. BIST schemes are typically classified into two categories: off-line and on-line. Input vector monitoring concurrent BIST schemes are a class of on-line techniques that circumvent the problems appearing separately in on-line and in off-line BIST. The utilization of input vector monitoring concurrent BIST techniques provides the capability to perform testing at different stages, manufacturing, periodic off-line and concurrent online. The input vector monitoring concurrent BIST schemes proposed so far have targeted either exhaustive or pseudorandom testing separately. In this paper a novel input vector monitoring concurrent BIST scheme based on a pre-computed test set is presented. The proposed scheme can perform both concurrent on-line and off-line testing; therefore it can be equally well utilized for manufacturing and concurrent on-line testing in the field. The applicability of the scheme is validated with respect to the hardware overhead and the time required for completion of the test in benchmark circuits. To the best of our knowledge, the proposed scheme is the first to be presented in the open literature based on a pre-computed test set that can perform both concurrent on line and off-line testing.