Demo Data from VLDB 2026 / reviewers in the wild / expert
Raoul Strackx
dblp:97/7967
· DBLP profile ↗
14ranked-venue papers
5as first author
0since 2021 · last 2018
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Security and privacy · 12 · 5 first-authorSoftware engineering, systems software and programming languages · 2
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Network and information security
7 papers |
Hardware security and side channels · 85% Systems and software security · 15% | |
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Embedded and real-time systems · 50% Processor architecture and microarchitecture · 50% | |
| Software engineering, system software, and programming languages
1 paper |
Compilers and program optimization · 100% |
Topics — the 11 heaviest of 14, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware security and side channels
side-channel attack |
0.6 | 2 | 2018 | Foreshadow: Extracting the Keys to the Intel SGX Kingdom with Transient Out-of-Order Execution · USENIX Security Symposium 2018 Telling Your Secrets without Page Faults: Stealthy Page Table-Based Attacks on Enclaved Execution · USENIX Security Symposium 2017 |
Hardware security and side channels
trusted execution environments |
0.6 | 4 | 2018 | Nemesis: Studying Microarchitectural Timing Leaks in Rudimentary CPU Interrupt Logic · CCS 2018 Foreshadow: Extracting the Keys to the Intel SGX Kingdom with Transient Out-of-Order Execution · USENIX Security Symposium 2018 Telling Your Secrets without Page Faults: Stealthy Page Table-Based Attacks on Enclaved Execution · USENIX Security Symposium 2017 |
Hardware security and side channels
microarchitectural side channel |
0.3 | 1 | 2018 | Nemesis: Studying Microarchitectural Timing Leaks in Rudimentary CPU Interrupt Logic · CCS 2018 |
Hardware security and side channels › microarchitectural attacks
transient execution attack |
0.3 | 1 | 2018 | Foreshadow: Extracting the Keys to the Intel SGX Kingdom with Transient Out-of-Order Execution · USENIX Security Symposium 2018 |
Hardware security and side channels › trusted execution environments
state continuity |
0.2 | 1 | 2016 | Ariadne: A Minimal Approach to State Continuity · USENIX Security Symposium 2016 |
Systems and software security › language-based security
secure compilation |
0.2 | 1 | 2015 | Secure Compilation to Protected Module Architectures · ACM Trans. Program. Lang. Syst. 2015 |
Compilers and program optimization
secure compilation |
0.2 | 1 | 2015 | Secure Compilation to Protected Module Architectures · ACM Trans. Program. Lang. Syst. 2015 |
Systems and software security
operating system security |
0.1 | 1 | 2012 | Fides: selectively hardening software application components against kernel-level or process-level malware · CCS 2012 |
Hardware security and side channels › trusted execution environments
Intel SGX |
0.1 | 1 | 2018 | Foreshadow: Extracting the Keys to the Intel SGX Kingdom with Transient Out-of-Order Execution · USENIX Security Symposium 2018 |
Processor architecture and microarchitecture › exception handling
interrupt handling |
0.1 | 1 | 2018 | Nemesis: Studying Microarchitectural Timing Leaks in Rudimentary CPU Interrupt Logic · CCS 2018 |
Hardware security and side channels › trusted execution environments
remote attestation |
0.0 | 1 | 2013 | Sancus: Low-cost Trustworthy Extensible Networked Devices with a Zero-software Trusted Computing Base · USENIX Security Symposium 2013 |
Methods — techniques the papers use, named apart from their topics
timing measurement · 0.7interrupt latency analysis · 0.7attack construction · 0.7full abstraction · 0.7formal proof · 0.7hardware-software co-design · 0.3
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2018 | Nemesis: Studying Microarchitectural Timing Leaks in Rudimentary CPU Interrupt LogicabstractRecent research on transient execution vulnerabilities shows that current processors exceed our levels of understanding. The prominent Meltdown and Spectre attacks abruptly revealed fundamental design flaws in CPU pipeline behavior and exception handling logic, urging the research community to systematically study attack surface from microarchitectural interactions. We present Nemesis, a previously overlooked side-channel attack vector that abuses the CPU's interrupt mechanism to leak microarchitectural instruction timings from enclaved execution environments such as Intel SGX, Sancus, and TrustLite. At its core, Nemesis abuses the same subtle microarchitectural behavior that enables Meltdown, i.e., exceptions and interrupts are delayed until instruction retirement. We show that by measuring the latency of a carefully timed interrupt, an attacker controlling the system software is able to infer instruction-granular execution state from hardware-enforced enclaves. In contrast to speculative execution vulnerabilities, our novel attack vector is applicable to the whole computing spectrum, from small embedded sensor nodes to high-end commodity x86 hardware. We present practical interrupt timing attacks against the open-source Sancus embedded research processor, and we show that interrupt latency reveals microarchitectural instruction timings from off-the-shelf Intel SGX enclaves. Finally, we discuss challenges for mitigating Nemesis-type attacks at the hardware and software levels. Jo Van Bulck, Frank Piessens, Raoul Strackx |
CCS | 3 |
| 2018 | Foreshadow: Extracting the Keys to the Intel SGX Kingdom with Transient Out-of-Order Execution
Jo Van Bulck, Marina Minkin, Ofir Weisse, Daniel Genkin, Baris Kasikci, Frank Piessens, Mark Silberstein, Thomas F. Wenisch, Yuval Yarom, Raoul Strackx |
USENIX Security Symposium | 10 |
| 2017 | Automatically Generating Secure Wrappers for SGX Enclaves from Separation Logic Specifications
Neline van Ginkel, Raoul Strackx, Frank Piessens |
APLAS | 2 |
| 2017 | Telling Your Secrets without Page Faults: Stealthy Page Table-Based Attacks on Enclaved Execution
Jo Van Bulck, Nico Weichbrodt, Rüdiger Kapitza, Frank Piessens, Raoul Strackx |
USENIX Security Symposium | 5 |
| 2016 | Ariadne: A Minimal Approach to State Continuity
Raoul Strackx, Frank Piessens |
USENIX Security Symposium | 1 |
| 2015 | Secure Compilation to Protected Module ArchitecturesabstractA fully abstract compiler prevents security features of the source language from being bypassed by an attacker operating at the target language level. Unfortunately, developing fully abstract compilers is very complex, and it is even more so when the target language is an untyped assembly language. To provide a fully abstract compiler that targets untyped assembly, it has been suggested to extend the target language with a protected module architecture—an assembly-level isolation mechanism which can be found in next-generation processors. This article provides a fully abstract compilation scheme whose source language is an object-oriented, high-level language and whose target language is such an extended assembly language. The source language enjoys features such as dynamic memory allocation and exceptions. Secure compilation of first-order method references, cross-package inheritance, and inner classes is also presented. Moreover, this article contains the formal proof of full abstraction of the compilation scheme. Measurements of the overhead introduced by the compilation scheme indicate that it is negligible. Marco Patrignani, Pieter Agten, Raoul Strackx, Bart Jacobs 0002, Dave Clarke 0001, Frank Piessens |
ACM Trans. Program. Lang. Syst. | 3 |
| 2014 | ICE: a passive, high-speed, state-continuity schemeabstractThe amount of trust that can be placed in commodity computing platforms is limited by the likelihood of vulnerabilities in their huge software stacks. Protected-module architectures, such as Intel SGX, provide an interesting alternative by isolating the execution of software modules. To minimize the amount of code that provides support for the protected-module architecture, persistent storage of (confidentiality and integrity protected) states of modules can be delegated to the untrusted operating system. But precautions should be taken to ensure state continuity: an attacker should not be able to cause a module to use stale states (a so-called rollback attack), and while the system is not under attack, a module should always be able to make progress, even when the system could crash or lose power at unexpected, random points in time (i.e., the system should be crash resilient). Raoul Strackx, Bart Jacobs 0002, Frank Piessens |
ACSAC | 1 |
| 2013 | Salus: Non-hierarchical Memory Access Rights to Enforce the Principle of Least Privilege
Niels Avonds, Raoul Strackx, Pieter Agten, Frank Piessens |
SecureComm | 2 |
| 2013 | Sancus: Low-cost Trustworthy Extensible Networked Devices with a Zero-software Trusted Computing Base
Job Noorman, Pieter Agten, Wilfried Daniels, Raoul Strackx, Anthony Van Herrewege, Christophe Huygens, Bart Preneel, Ingrid Verbauwhede, Frank Piessens |
USENIX Security Symposium | 4 |
| 2012 | Fides: selectively hardening software application components against kernel-level or process-level malwareabstractProtecting commodity operating systems against software exploits is known to be challenging, because of their sheer size. The same goes for key software applications such as web browsers or mail clients. As a consequence, a significant fraction of internet-connected computers is infected with malware. Raoul Strackx, Frank Piessens |
CCS | 1 |
| 2012 | Secure Compilation to Modern ProcessorsabstractWe present a secure (fully abstract) compilation scheme to compile an object-based high-level language to low-level machine code. Full abstraction is achieved by relying on a fine-grained program counter-based memory access protection scheme, which is part of our low-level target language. We discuss why standard compilers fail to provide full abstraction and introduce enhancements needed to achieve this goal. We prove that our enhanced compilation scheme provides full abstraction from our high-level source language to our low-level target language. Lastly, we show by means of a prototype implementation that our low-level language with fine-grained memory access control can be realized efficiently on modern commodity platforms. Pieter Agten, Raoul Strackx, Bart Jacobs 0002, Frank Piessens |
CSF | 2 |
| 2012 | Recent Developments in Low-Level Software Security
Pieter Agten, Nick Nikiforakis, Raoul Strackx, Willem De Groef, Frank Piessens |
WISTP | 3 |
| 2010 | Efficient Isolation of Trusted Subsystems in Embedded Systems
Raoul Strackx, Frank Piessens, Bart Preneel |
SecureComm | 1 |
| 2010 | Efficient and Effective Buffer Overflow Protection on ARM Processors
Raoul Strackx, Yves Younan, Pieter Philippaerts, Frank Piessens |
WISTP | 1 |