With the growing demand for computing power, new multicore architectures have emerged to provide better performance.Reducing their energy consumption is one of the main challenges in achieving high performance computing.Current research trends develop new software and hardware techniques to achieve the best performance and energy compromise.In this work, we investigate the effect of processor frequency scaling using Dynamic Voltage Frequency Scaling on performance and energy consumption for the WZ factorization.This factorization is implemented both without optimization techniques and with strip mining.This technique involves transforming the program loop to improve program performance.Based on time and energy tests, we have shown that for the WZ factorization algorithm, regardless of the presence of manual optimization, it pays to reduce the frequency to save energy without losing performance.The conclusion can be extended to analogous algorithmsalso having a high ratio of memory access to computational operations.

Scalability is an important aspect related to time and energy savings on modern multicore architectures.In this paper, we investigate and analyze scalability in terms of time and energy.We compare the execution time and consumption energy of the LU factorization (without pivoting) and Cholesky, both with Math Kernel Library (MKL) on a multicore machine.In order to save the energy of these multithreaded factorizations, the dynamic voltage and frequency scaling (DVFS) technique was used.This technique allows the clock frequency to be scaled without changing the implementation.An experimental scalability evaluation was performed on an Intel Xeon Gold multicore machine, depending on the number of threads and the clock frequency.Our test results show that scalability in terms of the execution time expressed by the Speedup metric has values close to a linear function with an increase in the number of threads.In contrast, scalability in terms of the energy consumed expressed by the Greenup metric has values close to a logarithmic function with an increase in the number of threads.Both kinds of scalability depend on the clock frequency settings and the number of threads.

High-level loop transformations are a key instrument to effectively exploit the resource in modern architectures.Energy consumption on multi-core architectures is one of the major issues connected with high-performance computing.We examine the impact of four loop transformation strategies on performance and energy consumption.The investigated strategies include: loop fission, loop interchange (permutation), stripmining, and loop tiling.Additionally, a column-wise and row-wise store formats for dense matrices are considered.Parallelization and vectorization are implemented using OpenMP directives.As a test, the WZ factorization algorithm is used.The comparison of selected strategies of the loop transformation is done for Intel architecture, namely Cascade Lake.It has been shown that for WZ factorization, which is an example of an application in which we can use the loop transformation, optimization towards highperformance can also be an effective strategy for improving energy efficiency.Our results show also that block size selection in loop tilling has a significant impact on energy consumption.