The paper proposes a novel Electrochemical Impedance Spectroscopy methodology that takes into account the nonlinearties present in the battery. For this purpose, the current-voltage relationship of the cell is modeled in discrete domain as a Volterra filter and the linear part of the nonlinear model is efficiently estimated using Orthogonal Periodic Sequences. Preliminary experimental results involving six lithium-ion cells show the soundness of the proposed approach also in comparison with the classical method.

This paper reports the methodology and results of the test campaign performed in the context of the development of the Low Complexity Enhancement Video Coding (LCEVC) ISO standard. LCEVC is a video coding technology that can be applied in conjunction to any other single-layer video coding technology to re-encode the residuals between the original video and its compressed representation. The first part of the paper describes the methodology for the verification tests: Requirements, Test Conditions, Test Sequences, Test Methods (Metrics); the second one reports the results of the objective and subjective tests carried out applying such methodology. The bitrate savings achieved with LCEVC when used in conjunction with four video codecs (AVC, HEVC, EVC, VVC) are reported.

Healthy sleep is required for sufficient restoration of the human body and brain. Therefore, in the case of sleep disorders, appropriate therapy should be applied timely, which requires a prompt diagnosis. Traditionally, a sleep diary is a part of diagnosis and therapy monitoring for some sleep disorders, such as cognitive behaviour therapy for insomnia. To automatise sleep monitoring and make it more comfortable for users, substituting a sleep diary with a smartwatch measurement could be considered. With the aim of providing accurate results, a study with a total of 30 night recordings was conducted. Objective sleep measurement with a Samsung Galaxy Watch 4 was compared with a subjective approach (sleep diary), evaluating the four relevant sleep characteristics: time of getting asleep, wake up time, sleep efficiency (SE), and total sleep time (TST). The performed analysis has demonstrated that the median difference between both measurement approaches was equal to 7 and 3 minutes for a time of getting asleep and wake up time correspondingly, which allows substituting a subjective measurement with a smartwatch. The SE was determined with a median difference between the two measurement methods of 5.22%. This result also implicates a possibility of substitution. Some single recordings have indicated a higher variance between the two approaches. Therefore, the conclusion can be made that a substitution provides reliable results primarily in the case of long-term monitoring. The results of the evaluation of the TST measurement do not allow to recommend substitution of the measurement method.

The Low Complexity Enhancement Video Coding (LCEVC) specification is a recent standard approved by the ISO/IEC JTC 1/SC 29/WG04 (MPEG) Video Coding. The main goal of LCEVC is to provide a standalone toolset for the enhancement of any other existing codec. It works on top of other coding schemes, resulting in a multi-layer video coding technology, but unlike existing scalable video codecs, adds enhancement layers completely independent from the base video. The LCEVC technology takes as input the decoded video at lower resolution and adds up to two enhancement sub-layers of residuals encoded with specialized low-complexity coding tools, such as simple temporal prediction, frequency transform, quantization, and entropy encoding. This paper provides an overview of the main features of the LCEVC standard: high compression efficiency, low complexity, minimized requirements of memory and processing power.

Normal breathing during sleep is essential for people’s health and well-being. Therefore, it is crucial to diagnose apnoea events at an early stage and apply appropriate therapy. Detection of sleep apnoea is a central goal of the system design described in this article. To develop a correctly functioning system, it is first necessary to define the requirements outlined in this manuscript clearly. Furthermore, the selection of appropriate technology for the measurement of respiration is of great importance. Therefore, after performing initial literature research, we have analysed in detail three different methods and made a selection of a proper one according to determined requirements. After considering all the advantages and disadvantages of the three approaches, we decided to use the impedance measurement-based one. As a next step, an initial conceptual design of the algorithm for detecting apnoea events was created. As a result, we developed an activity diagram on which the main system components and data flows are visually represented.

Homomorphic deconvolution is applied to sEMG signals recorded during walking. Gastrocnemius lateralis and tibialis anterior signals were acquired according to SENIAM recommendation. MUAP parameters like amplitude and scale were estimated, whilst the MUAP shape parameter was fixed. This features a useful time-frequency representation of sEMG signal. Estimation of scale MUAP parameter was verified extracting the mean frequency of filtered EMG signal, extracted from the scale parameter estimated with two different MUAP shape values.

Food traceability is a fundamental requirement for the agriculture of the future. The project proposed in this work uses smartphones with NFC technology in every phase of the food supply chain (production, processing, distribution and consumption) bringing the information to the final consumer. The architecture consists of a complex identification system, which transmits data to a database through apps on android smartphones during all phases of the production process. Data storage in the cloud allows information to be shared among farmers involved in the same production chain, with agricultural consortia with government institutions and with final consumers.

Lithium-ion battery pack performance and longevity can be severely affected by cell-to-cell variations. Statistical modeling is an important tool for optimization of performance and safety of battery packs. This work presents uncertainty quantification of Lithium-ion battery performance, in particular sensitivity analysis. This analysis is based on calculation of Sobol' indices from a surrogate model, based on Polynomial Chaos Expansion. Performance is compared with Monte Carlo simulations.

The increasing complexity of VLSI digital systems has dramatically supported system-level representations in modeling and design activities. This evolution makes often necessary a compliant rearrangement of the modalities followed in validation and analysis tasks, as in the case of power performances estimation. Nowadays, transaction-level paradigms are having a wider and wider consideration in the research on electronic system-level design techniques. With regard to the available modeling resources, the most relevant framework is probably the transaction-level extension of the SystemC language (SystemC/TLM), which therefore represents the best platform for defining transaction-level design techniques. In this paper we present a macro-modeling power estimation methodology valid for SystemC/TLM prototypes and of general applicability. The present discussion illustrates the implementation modalities of the proposed approach, verifying its effectiveness through a comparison with RTL estimation techniques.

The common algorithm used to control DC-AC switching power converters is Pulse Width Modulation. This work presents the use of Dynamic Oversamplig Ratio Sigma- Delta modulators for the control of the switches of DC-AC switching power converters. The proposed control algorithm presents the advantage of a reduction of conducted electromagnetic interferences with respect to Pulse Width Modulation. A prototype of a DC-AC switching power converter has been implemented.

Fast design and verification is becoming a necessity for electronic industry to hit the more and more restrictive market requests. The model-based approach represents a possible way to ensure fast and flexible system design and verification, allowing a quantitative exploration of the space of solutions. In this paper the SystemC environment has been used to design a complete TLM model of IEEE 802.15.4 standard. The TLM abstraction level design allows high simulation speed, high-level performance analysis and an easy evaluation of a large set of performance parameters.

This work reports the design of an embedded system using WirelessUSB technology. The paper includes the most important characteristics of the communication protocol and the results of some tests to verify the performances of the network. An analytical model of the BER as a function of the transmitter output power and distances between the devices has been derived.

The paper presents a new dynamic power management architecture for a system-on-chip. The power state machine, which describes the status of the core, follows the recommendations of the ACPI (advanced configuration and power interface) standard. The algorithm controls the power states of each block on the basis of battery status, chip temperature and a user defined task priority.

The SystemC modules of the link manager layer and baseband layer have been designed in this work at behavioral level to analyze the performance of the Bluetooth standard. In particular the probability of the creation of a piconet in the presence of noise in the channel and the power reduction using the sniff and hold mode have been investigated.

Bus performances are extremely important in a platform-based design. System Level analysis of bus performances gives important information for the analysis and choice between different architectures driven by functional, timing and power constraints of the System-on-Chip. This paper presents the effect of different arbitration algorithms and bus usage methodologies on the bus AMBA AHB performances in terms of effective throughput and power dissipation. SystemC and VHDL models have been developed and simulations have been performed.

The concept of a SOC platform architecture introduces the concept of a communication infrastructure. In the transaction-level, a finite set of architecture components (memories, arithmetic units, address generators, caches, etc) communicate among each other over shared resources (buses). Until recently, modeling architectures required pin-level hardware descriptions, typically coded in RTL. Great effort is required to design and verify the models, and simulation at this level of detail is tediously slow. Transaction level modeling is the solution. Transaction level models (TLMs) effectively create an executable platform model that simulates orders of magnitude faster than a RTL model.

High level design methodologies are needed to overcome the complexity of system on chip design. In this paper, the SystemC environment has been used to design a Bluetooth transceiver. The high simulation speed allowed a high level performance analysis of the IP developed and the definition of an algorithm for selecting the best packet type in the presence of channel noise.

With the shrinking of device sizes, random device variations become a key factor limiting the performances of high-resolution complementary metal-oxide-semiconductor (CMOS) current-steering digital-to-analog converters (DACs). In this paper, we present a novel design methodology based on statistical modeling of MOS transistor drain current that allows designers to explore different DAC architectures and to study the effects of technological variations on system performance without using time-consuming Monte Carlo simulations. This technique requires as a first step the estimation of the mean value and the autocorrelation function of a single stochastic process. This stochastic process models the device drain current and summarizes all the random sources associated with the process/device variations since the current represents the effect of all of them. Subsequently, on the basis of such an approach, a behavioral model of current-steering DACs has been developed. Finally, the statistical simulation of static performances such as differential nonlinearity and integral nonlinearity has been carried out for different DAC architectures based on the behavioral model previously derived.

A novel current-mode CMOS circuit is used to implement fuzzy partition membership functions. The architecture, circuit and cadence spectra simulations are presented.

A rigorous formulation of the parametric yield for very large scale integration (VLSI) designs including the mismatch effect is proposed. The theory has been carried out starting from a general statistical model relating random variations of device parameters to the stochastic behavior of process parameters. The model predicts a dependence of correlation, between devices fabricated in the same die, on their dimensions and mutual distances so that mismatch between equally designed devices can be considered as a particular case of such a model. As an application example, a new model for the autocorrelation function is proposed from which the covariance matrix of the parameters is derived. By assuming a linear approximation, a suitable formulation of the parametric yield for VLSI circuit design is obtained in terms of the covariance matrix of parameters.

The ability of a neural network to learn from experience can be viewed as closely related to its approximating properties. By assuming that environment is essentially stochastic it follows that neural networks should be able to approximate stochastic processes. The aim of this paper is to show that some classes of artificial neural networks exist such that they are capable of providing the approximation, in the mean square sense, of prescribed stochastic processes with arbitrary accuracy. The networks so defined constitute a new model for neural processing and extend previous results concerning approximating capabilities of artificial neural networks.

Adequate analytical device models for circuit simulators are required in the design of IC's, especially in analog design, because the reliability of simulation results is closely related to model accuracy. A semiempirical approach to device modeling offers many advantages over physics-based modeling, in which complex equations have to be solved, and seems to be the most appropriate for circuit simulation. However as this approach is not founded on a rigorous mathematical theory no general methodologies are available for its implementation. Furthermore, device models currently used in circuit simulators are derived by neglecting randomness in experimental data. This assumption is not realistic for mass-produced IC's where technological tolerances cause variations in the measured data, even if they are obtained using the same experimental conditions. The aim of this work is to develop a new scheme for semiempirical device modeling founded on the rigorous mathematical framework of "regularization theory" and to suggest a parameter extraction method based on Bayesian parameter estimation, which takes into account randomness in data. The application of the method to the development of an accurate model for MOS transistors shows the validity of the proposed theoretical approach which is further confirmed by extensive analysis of experimental data.