Side-channel resilience is a critical requirement for cryptographic accelerators. However, current validation approaches rely heavily on costly, measurement-based testing, which is typically applicable only at the final stages of the design flow. This reliance on physical prototypes is aggravated by the lack of integrated security analysis in fragmented toolchains. To address these challenges, we introduce the HWSEC-OSS Framework, a comprehensive open-source platform designed to streamline the security validation of hardware designs. The framework integrates a complete digital design flow with a pre-silicon Side-Channel Analysis (SCA) module based on Hamming-distance power modeling. We demonstrate the effectiveness of the framework by identifying leakage sources in an EdDSA25519 implementation, exhibiting a strong correlation between simulation-based results and measurements from a physical FPGA prototype. Furthermore, we apply the flow to a hardware implementation of ML-KEM, demonstrating scalability to Post-Quantum Cryptography (PQC). By providing an integrated environment for early security feedback, this work constitutes a fast, cost-effective solution for hardware security validation.

The Keccak core is a fundamental cryptographic primitive widely used in post-quantum cryptography to ensure security against emerging quantum-computing attacks. Secure software implementations rely on masking schemes to mitigate side-channel leakage, but these protections introduce significant overhead, which is particularly impactful on resource-constrained microcontrollers and further exacerbated by micro-architectural leakages. To date, publicly available masked Keccak implementations do not achieve both efficiency and robustness against such leakages. This work presents an optimized software implementation providing 1st-order side-channel protection, as well as the first efficiency-oriented 2nd-order implementation, surpassing previous solutions in performance. Both implementations target the ARM Cortex-M4 microcontroller and satisfy constraints to prevent micro-architectural leakages. A public repository provides the source code and a labeled dataset of 500K+500K traces, enabling reproducibility. Benchmarks show a 44.1% improvement over previously reported first-order implementations.

Physical Unclonable Functions (PUFs) are a very useful resource in cryptography with many applications ranging from system authentication to secret key generation. Side-channel attacks (SCAs) are a major concern in any physical implementation of a cryptographic module, and PUFs are no exception. Electromagnetic (EM) leakage from the implementation of a ring-oscillator-based PUF (RO-PUF) can be exploited to retrieve sensitive information that compromises the security of the cryptographic scheme incorporating the PUF. In this paper, we analyse the EM leakage of an RO-PUF implemented on FPGA, highlight its main vulnerabilities, and propose alternative countermeasures and architectures to mitigate the threat of this type of attack. Furthermore, we evaluate the cost in terms of area overhead of the proposed implementations compared to the original design.

The adoption of Post-Quantum Cryptography over the security network layer, such as Transport Layer Security, poses significant challenges, particularly in the context of Internet of Things (IoT) devices, where power and area constraints frequently limit the adoption of hardened security features. In addressing this challenge, hardware-based Secure Elements become a crucial component in facilitating cryptographic operations and storing secret keys within these frameworks. However, the design and validation of such hardware modules require substantial time investment. Consequently, this can result in the allocation of time that could be utilized for the development of other essential components of the Post-Quantum Transition. In this context, the present work proposes a methodology for the integration of Secure Elements on IoT devices, with the objective of reducing the time required for design and validation. To this end, two distinct categories of IoT devices (microcontrollers and embedded processors) have been employed to encompass the broadest possible range of IoT devices. The outcome of this study is the delivery of an open-source cryptographic library that can be deployed in any type of IoT devices. This library facilitates the implementation of Post-Quantum Cryptography in Secure Elements enabling crypto-agility and ensuring a smooth PostQuantum transition for IoT.

In recent years, numerous attacks have appeared that aim to steal secret information from their victim using the power side-channel vector, yet without direct physical access. These attacks are called Remote Power Attacks or Remote Power Analysis, utilizing resources that are natively present inside the victim environment. However, there is no unified definition about the limitations that a power attack requires to be defined as remote. This paper aims to propose a unified definition and concrete threat models to clearly differentiate remote power attacks from non-remote ones. Additionally, we collect the main remote power attacks performed so far from the literature, and the principal proposed countermeasures to avoid them. The search of such countermeasures denoted a clear gap in preventing remote power attacks at the technical level. Thus, the academic community must face an important challenge to avoid this emerging threat, given the clear room for improvement that should be addressed in terms of defense and security of devices that work with private information.

Post-quantum cryptographic algorithms have emerged to secure communication channels between electronic devices faced with the advent of quantum computers. The performance of post-quantum cryptographic algorithms on embedded systems has to be evaluated to achieve a good trade-off between required resources (area) and timing. This work presents two optimized implementations to speed up the NTRUEncrypt algorithm on a system-on-chip. The strategy is based on accelerating the most time-consuming operation that is the truncated polynomial multiplication. Hardware dedicated modules for multiplication are designed by exploiting the presence of consecutive zeros in the coefficients of the blinding polynomial. The results are validated on a PYNQ-Z2 platform that includes a Zynq-7000 SoC from Xilinx and supports a Python-based programming environment. The optimized version that exploits the presence of double, triple, and quadruple consecutive zeros offers the best performance in timing, in addition to considerably reducing the possibility of an information leakage against an eventual attack on the device, making it practically negligible.

This paper describes a design methodology to implement on FPGAs piecewise-affine (PWA) functions based on representation methods from the lattice theory. An off-line automatic processing starts at the algorithmic formulation of the problem, obtains the parameters required by a parameterized digital architecture, and ends with the bitstream to program an FPGA. The methodology has been proven to implement PWA functions on Xilinx FPGAs. The results are compared with other approaches for FPGA implementations of PWA functions.