Transient fault recovery is important in processor availability. However, significant silicon or performance over-heads are characteristics of existing techniques. We uncover an opportunity to reduce the overheads dramatically in modern processors that appears as a side-effect of introducing hardware multithreading to improve performance. We observe that threads are usually short code sequences with no branches and few memory side-effects, which means that the number of checkpoints is small and constant. In addition, the state structures of a thread already presented in hardware can be reused to provide check pointing. In this paper, we demonstrate this principle of using a hardware/software co-design called Rethread, which features compiler-generated code annotations and automatic recovery in hardware by restarting threads. This approach provides the ability to recover from transient faults without dedicated hardware. Moreover, results show performance degradation under both fault-free condition (less than 5%) and as a function of fault rate.

This paper designs and implements the Redundant Multi-Threading (RMT) in a Data-flow scheduled MultiThreaded (DMT) multicore processor, called Data-flow scheduled Redundant Multi-Threading (DRMT). Meanwhile, It presents Asynchronous Output Comparison (AOC) for RMT techniques to avoid fault detection related inter-core communication and alleviate the performance and hardware overheads induced by output comparison. Results show that the performance overhead of DRMT is less than 60% even when the number of threads is four times the number of processing elements. Also the performance and hardware overheads of AOC are insignificant.

High-level simulation is becoming commonly used for design space exploration of many-core systems. We have been working on high-level simulation techniques for the microthreaded many-core architecture at the University of Amsterdam. In previous work different levels of high-level simulation for instruction execution have been proposed, where the objective of every level is to keep the highest possible abstraction in order to achieve the least complexity and highest simulation speed with a compromise on the amount of accuracy. In this article we propose a new breakthrough in abstraction by simulating entire components in applications using analytical models. This simulation technique greatly reduces the complexity of the simulator and increases the simulation speed by orders of magnitude compared to the other levels of the high-level simulator, without affecting the simulation accuracy.

When hardware cache coherence scales to many cores on chip, over saturated traffic of the shared memory system may offset the benefit from massive hardware concurrency. In this article, we investigate the cost of a write-update protocol in terms of on-chip memory network traffic and its adverse effects on the system performance based on a multithreaded many-core architecture with distributed caches. We discuss possible software and hardware solutions to alleviate the network pressure. We find that in the context of massive concurrency, by introducing a write-merging buffer with 0.46% area overhead to each core, applications with good locality and concurrency are boosted up by 18.74% in performance on average. Other applications also benefit from this addition and even achieve a throughput increase of 5.93%. In addition, this improvement indicates that higher levels of concurrency per core can be exploited without impacting performance, thus tolerating latency better and giving higher processor efficiencies compared to other solutions.

To harness the potential of CMPs for scalable, energy-efficient performance in general-purpose computers, the Apple-CORE project has co-designed a general machine model and concurrency control interface with dedicated hardware support for concurrency management across multiple cores. Its SVP interface combines dataflow synchronisation with imperative programming, towards the efficient use of parallelism in general-purpose workloads. The corresponding hardware implementation provides logic able to coordinate single-issue, in-order multi-threaded RISC cores into computation clusters on chip, called Microgrids. In contrast with the traditional "accelerator" approach, Microgrids are intended to be used as components in distributed systems on chip that consider both clusters of small cores and optional larger cores optimized towards sequential performance as system services shared between applications. The key aspects of the design are asynchrony, i.e. the ability to tolerate operations with irregular long latencies, a scale-invariant programming model, a distributed vision of the chip's structure, and the transparent performance scaling of a single program binary code across multiple cluster sizes. This paper describes the execution model, the core micro-architecture, its realization in a many-core, general-purpose processor chip and its software environment. The reference chip parameters include 128 cores, a 4 MB on-chip distributed cache network and four DDR3-1600 memory channels. This paper presents cycle-accurate simulation results for various key algorithmic and cryptographic kernels. The results show good efficiency in terms of the utilization of hardware despite the high-latency memory accesses and good scalability across relatively large clusters of cores.

Microgrid CMPs, that is based on microthreaded processors, use hardware scheduling and synchronisation and have structures to support this that are distributed, fully scalable and which can support hundreds of microthreads per processor and their associated microcontexts. The chip has locality in communication wherever possible, and supports a globally-asynchronous locally-synchronous (GALS) design approach, where all its global communications are asynchronous, creating independent clocking domains for each microthreaded processor. Each microthreaded processor has its own instruction window and local register file, both of which are fully scalable. Any remote access is fully decupled from the pipeline operations including memory. This paper introduces the microgrid CMP architecture model and discusses in general terms how our approach meets the challenges facing CMP architectures. It also summarizes microgrid CMP performance simulations published elsewhere and presents a local scheduler and the microthreaded in-order pipeline.

Most microprocessor chips today use an out-of-order instruction execution mechanism. This mechanism allows superscalar processors to extract reasonably high levels of instruction level parallelism (ILP). The most significant problem with this approach is a large instruction window and the logic to support instruction issue from it. This includes generating wake-up signals to waiting instructions and a selection mechanism for issuing them. Wide-issue width also requires a large multi-ported register file, so that each instruction can read and write its operands simultaneously. Neither structure scales well with issue width leading to poor performance relative to the gates used. Furthermore, to obtain this ILP, the execution of instructions must proceed speculatively. An alternative, which avoids this complexity in instruction issue and eliminates speculative execution, is the microthreaded model. This model fragments sequential code at compile time and executes the fragments out of order while maintaining in-order execution within the fragments. The only constraints on the execution of fragments are the dependencies between them, which are managed in a distributed and scalable manner using synchronizing registers. The fragments of code are called microthreads and they capture ILP and loop concurrency. Fragments can be interleaved on a single processor to give tolerance to latency in operands or distributed to many processors to achieve speedup. The implementation of this model is fully scalable. It supports distributed instruction issue and a fully scalable register file, which implements a distributed, shared-register model of communication and synchronization between multiple processors on a single chip. This paper introduces the model, compares it with current approaches and presents an analysis of some of the implementation issues. It also presents results showing scalable performance with issue width over several orders of magnitude, from the same binary code.

Although a number of learning management systems are running on the Internet, it is clear that they are not able to efficiently meet users' requirements, e.g. dynamically create and control learning activities and processes, and efficiently describe and use the semantics of learning objects and content. In this paper, we propose a schema-driven methodology to design a general learning management system supporting XML and Web-services technologies. This system is driven and controlled by schema processors, which provide the ability for users to freely generate and manage learning procedures such as replace learning activities. In addition, it can interact with legacy systems. We represent the procedures of controlling learning activities through schema management, such as dynamically establishing and allocating the main directories (e.g. the learning activity directory) from the central databases (e.g. the learning activity database) to a user in terms of his/her roles, sub-roles and requirements. This system can greatly improve the capabilities of existing learning management systems.

Propagating the clock through large networks and providing correct functioning of the system is a serious engineering problem. The clock appears at different moments for two different physical points/spl minus/clock skew problem. While the clock skew can be neglected for small systems, it results in major problems when building large concurrent networks. To overcome such problems the authors believe that the absolute solution is to eliminate the notion of clocking entirely throughout by adopting asynchronous design techniques. Packet switches are familiar components of concurrent architectures and a good example to illustrate asynchronous design. The paper describes the asynchronous implementation of three basic building blocks for asynchronous packet routers and also demonstrates asynchronous design techniques for VLSI design.>

This paper presents results concerning the design and testing of a fast network chip (the MPI) for parallel computers. We briefly introduce the theoretical results on which the MPI chip design was based and describe its architecture. The chip has been fabricated and tested in small prototype system. Based on parameters measured using this prototype and a simulator implemented at the logic level we have been able to accurately model the performance of larger networks based on this chip under a variety of synthetic loads. Extensive results are presented based on these simulations

In order to provide an arbitrary and fully dynamic connectivity in a network of processors, transport mechanisms must be implemented, which provide the propagation of data from processor to processor, based on addresses contained within a packet of data. Such data transport mechanisms must satisfy a number of requirements - deadlock and livelock freedom, good hot-spot performance, high throughput and low latency. This paper proposes a solution to these problems, which allows deadlock free, adaptive, high throughput packet routing to be implemented on networks of processors. Examples are given which illustrate the technique for 2-D array and toroidal networks. An implementation of this scheme on arrays of transputers is described. The scheme also serves as a basis for a very low latency routing strategy named the mad postman, a detailed implementation of which is described here as well.

Abstract A Pascal syntax directed screen editor, designed to run under PNX on an ICL Perq workstation is presented. The editor (Eliot) offers a structured approach to text editing and provides complete Pascal syntax checking. The exceptional graphic capabilities of the Perq are used to good effect in providing an efficient user interface by way of a hierarchy of pop‐up menus. Using this interface, skeletal programs may be entered down to the assignment statement, or procedure call level without recourse to the keyboard, selections being made from menus using a graphics tablet and puck. Eliot encourages block structured programs with nested blocks by the use of a tree structured menu, representing the program structure. This allows for efficient movement around the program, again using the tablet and puck. Syntax checking is performed continually with errors reported and highlighted immediately for correction at will. For further error checking a variable scan option can be invoked which lists details of variable names which are not declared, or declared more than once, or declared and not used at all.

Methods of implementing fast radix 2 transforms on array processors are considered. The complexity of arithmetic and data routing operations is analyzed for the methods given. It is shown that all methods give an O(P) speed-up in the arithmetic operations for a P processor array. However the methods incur an overhead in data organization. Theorems are presented that prove one method to be superior in minimizing this overhead for transforms of length N > P.

Some properties of k-dimensional cyclic networks are derived and used to give some algorithmic timings for the transposition of rectangular sets of data in an array processor's memory. General results are produced which can be applied to ICL's distributed array processor (DAP).