Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data.
VLDB 2026 Research / reviewers in the wild / expert

Bradley Warren Smith

dblp:98/2425 · DBLP profile ↗
← Back
1ranked-venue papers
1as first author
0since 2021 · last 1985
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Processor architecture and microarchitecture · 44% Parallel and multicore computing · 44% Performance modeling and evaluation · 13%

Topics — the 2 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Parallel and multicore computing › parallel architecture
parallel processor design		 0.011985
Models for Use in the Design of Macro-Pipelined Parallel Processors · ISCA 1985
Processor architecture and microarchitecture
pipelining		 0.011985
Models for Use in the Design of Macro-Pipelined Parallel Processors · ISCA 1985

Methods — techniques the papers use, named apart from their topics

queueing model · 0.0analytical modeling · 0.0
YearPublicationVenuePosition
1985 Models for Use in the Design of Macro-Pipelined Parallel Processors
abstract
article Models for use in the design of macro-pipelined parallel processors Share on Authors: Bradley Warren Smith PASM Parallel Processing Laboratory, School of Electrical Engineering, Purdue University, West Lafayette, IN PASM Parallel Processing Laboratory, School of Electrical Engineering, Purdue University, West Lafayette, INView Profile , Howard Jay Siegel PASM Parallel Processing Laboratory, School of Electrical Engineering, Purdue University, West Lafayette, IN PASM Parallel Processing Laboratory, School of Electrical Engineering, Purdue University, West Lafayette, INView Profile Authors Info & Claims ACM SIGARCH Computer Architecture NewsVolume 13Issue 3June 1985 pp 116–123https://doi.org/10.1145/327070.327140Online:01 June 1985Publication History 0citation294DownloadsMetricsTotal Citations0Total Downloads294Last 12 Months4Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access
Bradley Warren Smith, Howard Jay Siegel
 ISCA1