Full-duplex (FD) wireless can significantly enhance spectrum efficiency but requires effective self-interference (SI) cancellers. RF SI cancellation (SIC) via frequency-domain equalization (FDE), where bandpass filters channelize the SI, is suited for integrated circuits (ICs). In this paper, we explore the limits and higher layer challenges associated with using such cancellers. We evaluate the performance of a custom FDE-based canceller using two testbeds; one with mobile FD radios and the other with upgraded, static FD radios in the PAWR COSMOS testbed. The latter is a lasting artifact for the research community, alongside a dataset containing baseband waveforms captured on the COSMOS FD radios, facilitating FD-related experimentation at the higher networking layers. We evaluate the performance of the FDE-based FD radios in both testbeds, with experiments showing 95 dB overall achieved SIC (52 dB from RF SIC) across 20 MHz bandwidth. We conduct network-level experiments for (i) uplink-downlink networks with inter-user interference, and (ii) heterogeneous networks with half-duplex and FD users, showing FD gains of$1.14\times $–$1.25\times $and$1.25\times $–$1.73\times $, respectively, confirming analytical results. We also evaluate the performance of an FD jammer-receiver, demonstrating a strong dependence on relative transmit power levels and modulation schemes.

Ubiquitous multicore processors nowadays rely on an integrated packet-switched network for cores to exchange and share data. The performance of these intra-chip networks is a key determinant of the processor speed and, at high core counts, becomes an important bottleneck due to scalability issues. To address this, several works propose the use of mm-wave wireless interconnects for intra-chip communication and demonstrate that, thanks to their low-latency broadcast and system-level flexibility, this new paradigm could break the scalability barriers of current multicore architectures. However, these same works assume 10+ Gb/s speeds and efficiencies close to 1 pJ/bit without a proper understanding of the wireless intra-chip channel. This paper first demonstrates that such assumptions do not hold in the context of commercial chips by evaluating losses and dispersion in them. Then, we leverage the system's monolithic nature to engineer the channel, this is, to optimize its frequency response by carefully choosing the chip package dimensions. Finally, we exploit the static nature of the channel to adapt to it, pushing efficiency-speed limits with simple tweaks at the physical layer. Our methods reduce the path loss and delay spread of a simulated commercial chip by 47 dB and $7.3\times $ , respectively, enabling intra-chip wireless communications over 10 Gb/s and only 3.1 dB away from the dispersion-free case.

Wireless Network-on-Chip (WNoC) has emerged as a promising alternative to conventional interconnect fabrics at the chip scale. Since WNoCs may imply the close integration of antennas, one of the salient challenges in this scenario is the management of coupling and interferences. This paper, instead of combating coupling, aims to take advantage of close integration to create arrays within a WNoC. The proposed solution is opportunistic as it attempts to exploit the existing infrastructure to build a simple reconfigurable beamforming scheme. Full-wave simulations show that, despite the effects of lossy silicon and nearby antennas, within-package arrays achieve moderate gains and beamwidths below 90°, a figure which is already relevant in the multiprocessor context.

Full-duplex (FD) wireless can significantly enhance spectrum efficiency but requires tremendous amount of self-interference (SI) cancellation. Recent advances in the RFIC community enabled wideband RF SI cancellation (SIC) in integrated circuits (ICs) via frequency-domain equalization (FDE), where reconfigurable RF filters are used to channelize the SI signal path. In [2], we designed and implemented an FDE-based RF canceller on a printed circuit board (PCB). We also presented an optimized canceller configuration scheme based on the derived canceller model, and extensively evaluated the performance of the FDE-based FD radios in a software-defined radio (SDR) testbed in different network settings.

Full-duplex (FD) wireless can significantly enhance spectrum efficiency but requires tremendous amount of self-interference (SI) cancellation. Recent advances in the RFIC community enabled wideband RF SI cancellation (SIC) in integrated circuits (ICs) via frequency-domain equalization (FDE), where RF filters channelize the SI signal path. Unlike other FD implementations, that mostly rely on delay lines, FDE-based cancellers can be realized in small-form-factor devices. However, the fundamental limits and higher layer challenges associated with these cancellers were not explored yet. Therefore, and in order to support the integration with a software-defined radio (SDR) and to facilitate experimentation in a testbed with several nodes, we design and implement an FDE-based RF canceller on a printed circuit board (PCB). We derive and experimentally validate the PCB canceller model and present a canceller configuration scheme based on an optimization problem. We then extensively evaluate the performance of the FDE-based FD radio in the SDR testbed. Experiments show that it achieves 95dB overall SIC (52dB from RF SIC) across 20MHz bandwidth, and an average link-level FD gain of 1.87x. We also conduct experiments in: (i) uplink-downlink networks with inter-user interference, and (ii) heterogeneous networks with half-duplex and FD users. The experimental FD gains in the two types of networks confirm previous analytical results. They depend on the users' SNR values and the number of FD users, and are 1.14x-1.25x and 1.25x-1.73x, respectively. Finally, we numerically evaluate and compare the RFIC and PCB implementations and study various design tradeoffs.

Wireless Network-on-Chip (WNoC) appears as a promising alternative to conventional interconnect fabrics for chip-scale communications. The WNoC paradigm has been extensively analyzed from the physical, network and architecture perspectives assuming mmWave band operation. However, there has not been a comprehensive study at this band for realistic chip packages and, thus, the characteristics of such wireless channel remain not fully understood. This work addresses this issue by accurately modeling a flip-chip package and investigating the wave propagation inside it. Through parametric studies, a locally optimal configuration for 60 GHz WNoC is obtained, showing that chip-wide attenuation below 32.6 dB could be achieved with standard processes. Finally, the applicability of the methodology is discussed for higher bands and other integrated environments such as a Software-Defined Metamaterial (SDM).

Full-duplex (FD) communication has the potential to substantially increase the throughput in wireless networks. However, the benefits of FD are still not well understood. In this paper, we characterize the FD rate gains in both single-channel and multi-channel use cases. For the single-channel case, we quantify the rate gain as a function of the remaining self-interference (SI) and signal-to-noise ratio values. We also provide a sufficient condition under which the sum of uplink and downlink rates on an FD channel is biconcave in the transmission power levels. Building on these results, we consider the multi-channel case. For that case, we introduce a new realistic model of a compact (e.g., smartphone) FD receiver and demonstrate its accuracy via measurements. We study the problem of jointly allocating power levels to different channels and selecting the frequency of maximum SI suppression, where the objective is to maximize the sum of the rates over uplink and downlink orthogonal frequency division multiplexing channels. We develop a polynomial time algorithm, which is nearly optimal, in practice, under very mild restrictions. To reduce the running time, we develop an efficient nearly optimal algorithm under the high SINR approximation. Finally, we demonstrate via numerical evaluations the capacity gains in different use cases and obtain insights into the impact of the remaining SI and wireless channel states on the performance.

A demonstration of a real-time full-duplex wireless link is presented, in which a pair of full-duplex transceivers perform simultaneous transmission and reception on the same frequency channel. A full-duplex transceiver is composed of a custom-designed small-form-factor analog self-interference canceller, and a digital self-interference cancellation implementation is integrated with the National Instruments Universal Software Radio Peripheral (USRP). An adaptive analog self-interference canceller tuning mechanism adjusts to environmental changes. We demonstrate the practicality and robustness of the full-duplex wireless link through the National Instruments LabVIEW interface.

Full-duplex communication has the potential to substantially increase the throughput in wireless networks. However, the benefits of full-duplex are still not well understood. In this paper, we characterize the full-duplex rate gains in both single-channel and multi-channel use cases. For the single-channel case, we quantify the rate gain as a function of the remaining self-interference and SNR values. We also provide a sufficient condition under which the sum of uplink and downlink rates on a full-duplex channel is concave in the transmission power levels. Building on these results, we consider the multi-channel case. For that case, we introduce a new realistic model of a small form-factor (e.g., smartphone) full-duplex receiver and demonstrate its accuracy via measurements. We study the problem of jointly allocating power levels to different channels and selecting the frequency of maximum self-interference suppression, where the objective is maximizing the sum of the rates over uplink and downlink OFDM channels. We develop a polynomial time algorithm which is nearly optimal under very mild restrictions. To reduce the running time, we develop an efficient nearly-optimal algorithm under the high SINR approximation. Finally, we demonstrate via numerical evaluations the capacity gains in the different use cases and obtain insights into the impact of the remaining self-interference and wireless channel states on the performance.

RF self-interference cancellation (SIC) relaxes duplexer isolation requirements in frequency- division-duplex (FDD) radios, enabling compact/tunable duplexers. RF SIC is also critical for full-duplex radios where extremely-high levels of SIC must be achieved, necessitating SIC at various points in the receiver chain. While active RF SIC is potentially compact and highly reconfigurable, the use of active circuitry in the canceller introduces noise, distortion and power dissipation challenges. Furthermore, and particularly for fully-integrated silicon-based SIC implementations, the bandwidth (BW) of RF SIC is limited by the frequency selectivity of the antenna interface and the wireless self-interference channel. In this paper, we present recent developments in fully-integrated RF SIC techniques that address these challenges.

The automatic frequency calibration (AFC) technique is routinely used in the wideband frequency synthesizers which contain multiple voltage-controlled oscillator (VCO) tuning curves. In this paper, a counter-based AFC design method is presented. The relationship between the AFC counting time and the VCO tuning curve characteristic is quantitatively analyzed. An AFC circuit which uses a time-to-digital converter (TDC) in the counting process is developed. Simulation results show that the proposed circuit significantly reduces the AFC calibration time while preserving the calibration accuracy. The simulated error-free AFC time of the proposed AFC is less than 3 µs.

A low power sigma-delta fractional-N frequency synthesizer for software-defined radio (SDR) implemented in a 0.13 μm CMOS process is presented, based on a dual-mode VCO (DMVCO) reconfigurable between wideband mode and quadrature mode, with optimized automatic frequency calibration (AFC). The proposed optimized AFC enables a more accurate band selection as well as a lower power for a dual-VCO PLL. A multi-phase counter (MPC) accelerates the calibration process without ruining the calibration accuracy. Simulated phase noise is -123 dBc/Hz at 1 MHz offset from a 1.8 GHz carrier. The spectral purity is better than 45 dBc from the output of mixer. The locking time of PLL is about 40 μs with an AFC time less than lOμs. The 0.4-6 GHz synthesizer consumes only 35 mW to 51 mW from a 1.2 V supply.

This paper presents a Sigma-Delta fractional-N frequency synthesizer for multi-standard receiver. The synthesizer's output range is 1.8~5.8GHz and covers the standards of DCS1800, WCDMA, TD-SCDMA, WLAN802. Ha/b/g and Bluetooth. Frequency planning is elaborately done to make sure the synthesizer meets specifications of standards mentioned above. QVCO with a proposed phase shifter is shown to have better phase noise performance and more stable oscillation. Simulated phase noise is -119dBc/Hz at 1-MHz offset from a 4.2GHz carrier. Its FOM ranges from 181 to 187. The frequency synthesizer is fabricated in TSMC 0.13um CMOS process. Average power consumption is 55.92mW.